Electrical Characteristics
Figure 4-4. PCI Output Timing
T
cyc_test
V_th
V_tl
CLK
V_test
V_test
V
oh
T_val
V_trise
OUTPUT
DELAY
T_val
OUTPUT
DELAY
V_tfall
V
ol
Tri-State
OUTPUT
T_on
T_off
Figure 4-5. PCI Input Timing
T_cyc_test
V_th
V_tl
V_test
V_test
V_test
T_h
CLK
T_su
V_th
V_tl
inputs
valid
INPUT
V_test
V_max
CS00292
NOTES:
1. See the timing measurement conditions in Figure 4-4.
2. Minimum times are measured at the package pin (not the test point) with the load circuit shown in the PCI-X
Electrical and Mechanical Addendum, Revision 2.0a. Maximum times are measured with the test point and
load circuit shown in PCI-X Electrical and Mechanical Addendum, Revision 2.0a.
Intel® 6702PXH 64-bit PCI Hub Datasheet
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INTEL [ INTEL ]
