Electrical Characteristics
Table 4-20. PCI and PCI-X Clock Timings
PCI-X 133
PCI-X 66
Min Max
15 20
PCI 66
PCI 33
Symbol
Parameter
Units Notes
Min
Max
Min
Max
Min
Max
Tcyc
CLK cycle time
(Average)
7.5
20
15
30
30
ns
1,3,4
1,3
∞
CLK Cycle Time
(Absolute
7.375
Minimum)
Thigh
Tlow
Tjit
CLK high time
CLK low time
3
3
6
6
6
6
11
11
ns
ns
ps
CLK Period Jitter
125
-125
4
200 -200
200
-200
4
300
-300
4
5
2
Slew Rate
—
CLK slew rate
1.5
1.5
4
1.5
1
V/ns
Spread Spectrum Requirements
fmod
Modulation
frequency
30
-1
33
0
30
-1
33
0
30
-1
33
0
kHz
%
fspread Frequency spread
NOTES:
1. For clock frequencies above 33 MHz, the clock frequency may not change beyond the spread-spectrum and
jitter limits except while RSTIN# is asserted.
2. This slew rate must be met across the minimum peak-to-peak portion of the clock waveform as shown in the
PCI-X Electrical and Mechanical Addendum, Revision 2.0a.
3. The minimum clock period must not be violated for any single clock cycle (i.e., accounting for all system
jitter).
4. Average Tcyc is measured over any 1 µs period of time and must include all sources of clock variation.
5. Period jitter is the deviation between any single period of the clock, Tcyc, and the average period of the clock,
Tcyc(average)
.
Intel® 6702PXH 64-bit PCI Hub Datasheet
175
INTEL [ INTEL ]
