Signal Description
The Intel® 6700PXH 64-bit PCI Hub only logs errors for cycles where it will do work. For
example, if a PCI cycle had an address parity error, and the Intel® 6700PXH 64-bit PCI Hub does
not assert PxDEVSEL# for that cycle, then that would not be logged as an error. Also, error
transaction logging on the PCI bus is decoupled from the error transaction logging on the PCI
Express* bus and this is possible because transaction error logging for a transaction that transits the
Intel® 6700PXH 64-bit PCI Hub, happens only once at the originating interface.
2.19.2.3
2.19.3
2.19.4
Error Escalation
To support error reporting on the PCI bus, the Intel® 6700PXH 64-bit PCI Hub implements
PxPERR# and PxSERR# signals. Also to escalate the PCI errors on to PCI Express*, the
Intel® 6700PXH 64-bit PCI Hub supports the ERR_COR, ERR_UNC, ERR_FATAL messages on
the PCI Express* bus.
SHPC Errors
Refer to the Standard Hot-Plug Controller and Subsystem Specification Revision 1.0 for details of
SHPC error logging and reporting implemented by the Intel® 6700PXH 64-bit PCI Hub. In
addition, the Intel® 6700PXH 64-bit PCI Hub provides for a way to route all SHPC interrupts to
platform firmware instead of to the OS, via a vendor-specific message on the PCI Express* bus.
Core Errors
Core errors in the Intel® 6700PXH 64-bit PCI Hub are SRAM soft errors. Data errors because of
SRAM errors are forwarded with poisoned data to the appropriate end point. If the end-point is an
internal device, then the data is dropped and an error message/completion (if required) signaled. If
the end point is on either the PCI or PCI Express* buses, the data is forwarded to the bus with the
data poisoned. This allows for the PCI/PCI Express* bus endpoints to determine the severity of the
error and deal with it appropriately. SRAM soft errors resulting in address parity errors are far more
severe. These transactions will be dropped and error message/completion generated.
Core errors will be logged with a single bit in the RAS_STS register for status. There will be a
RAS_IQE register to capture individual SRAM errors from various units.
2.19.5
Global Error Register
RAS_STS register captures status of all the first and next errors signaled from the PCI Express*
bus, PCI bus and core SRAM errors. Signaled errors correspond to only uncorrectable errors. For
both the first and next error groups, there is one bit for the PCI Express* bus, one for the PCI
bus(es) and one for all core SRAM errors.
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Intel® 6700PXH 64-bit PCI Hub Datasheet
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