Signal Description
Table 2-2. PCI Bus Interface A and B Signals (Sheet 2 of 2)
Signal
Type
Description
PAPCIRST#
PBPCIRST#
O
PCI Reset: The Intel® 6700PXH 64-bit PCI Hub asserts PxPCIRST# to reset
devices that reside on the secondary PCI bus. The Intel® 6700PXH 64-bit PCI
Hub asserts PxPCIRST# due to one of the following events:
•
•
RSTIN# is asserted.
The PCI Reset (bit 6) in the Bridge Control Register is set.
Connect to the RST# pin of the PCI slot(s).
PAPCIXCAP
PBPCIXCAP
I
Only relevant when Hot Plug Mode is disabled (HPx_SLOT[3] = 0) or when in
one-slot-no-glue hot plug mode (HPx_SLOT[3:0] = 1111).
PCI-X Capable: This signal indicates whether all devices on the PCI bus are
PCI-X devices, so that the Intel® 6700PXH 64-bit PCI Hub can switch into PCI-X
mode.
PAPCLKI
PBPCLKI
I
PCI Clock Input.
PAPCLKO[6:0]
PBPCLKO[6:0]
O
PCI Clock Output: These signals provide 33/66/100/133 MHz clock for a
PCI/PCI-X device. PxPCLKO[0] goes to slot or device #1, PxPCLKO[1] goes to
slot or device #2, etc. PxPCLKO[6] is connected to the PxPCLKI input. Unused
PCI Clock outputs should be turned off by BIOS and left as no connects on the
system board.
PAPERR#
PBPERR#
I/O
O
Parity Error: PxPERR# is driven by an external PCI device when it receives data
that has a parity error. Driven by the Intel® 6700PXH 64-bit PCI Hub when, as an
initiator it detects a parity error during a read transaction and as a target during
write transactions.
PAPLOCK#
PBPLOCK#
PCI Lock: This signal indicates an exclusive bus operation and may require
multiple transactions to complete. The Intel® 6700PXH 64-bit PCI Hub asserts
PxPLOCK# when it is doing exclusive transactions on the PCI bus. PxPLOCK# is
ignored when PCI masters are granted the bus. The Intel® 6700PXH 64-bit PCI
Hub does not propagate locked transactions upstream.
PAPME#
PBPME#
I
PCI Power Management Event: PCI bus power management event signal. This
is a shared open drain signal from all the PCI cards on the corresponding PCI
bus segment. This is a level sensitive signal that will be converted to a PME
event on the PCI Express* bus.
PAREQ_[5:0]#
PBREQ_[5:0]#
I
I
PCI Request: Request input into the Intel® 6700PXH 64-bit PCI Hub arbiter.
PASERR#
PBSERR#
System Error: PxSERR# can be pulsed active by any PCI device that detects a
system error condition except the Intel® 6700PXH 64-bit PCI Hub. The Intel®
6700PXH 64-bit PCI Hub samples PxSERR# as an input and conditionally
forwards it to the PCI Express* interface.
PASTOP#
PBSTOP#
I/O
I/O
Stop: PxSTOP# indicates that the target is requesting an initiator to stop the
current transaction.
PATRDY#
PBTRDY#
Target Ready: PxTRDY# indicates the ability of the target to complete the
current data phase of the transaction. A data phase is completed when both
PxTRDY# and PxIRDY# are sampled asserted. PxTRDY# is tri-stated from the
leading edge of PxPCIRST#. PxTRDY# remains tri-stated by the Intel® 6700PXH
64-bit PCI Hub until driven as a target.
Intel® 6700PXH 64-bit PCI Hub Datasheet
21
INTEL [ INTEL ]
