Signal Description
2.2
PCI/PCI-X Bus Interface
Table 2-2. PCI Bus Interface A and B Signals (Sheet 1 of 2)
Signal
Type
Description
PA133EN
PB133EN
I
Only relevant when Intel® 6700PXH 64-bit PCI Hub samples PxPCIXCAP at a
level indicating 133MHz PCI-X capability.
PCI-X 133 MHz Enable: Sets the maximum frequency capability of a PCI-X
mode 1 bus to either 100 MHz or 133 MHz.
This pin, when high, allows the PCI-X segment to run at a maximum 133 MHz
when in PCI-X mode 1. When low, the PCI-X segment is limited to a maximum
frequency of 100 MHz when in PCI-X mode 1.
PAAD[31:0]
PBAD[31:0]
I/O
I/O
PCI Address/Data: These signals are a multiplexed address and data bus.
During the address phase or phases of a transaction, the initiator drives a
physical address on PxAD[31:0]. During the data phases of a transaction, the
initiator drives write data, or the target drives read data.
PACBE_[3:0]#
PBCBE_[3:0]#
Bus Command and Byte Enables: These signals are a multiplexed command
field and byte enable field. During the address phase or phases of a transaction,
the initiator drives the transaction type on PxCBE_[3:0]#. For both read and write
transactions, the initiator drives byte enables on PxCBE_[3:0]# during the data
phases.
PADEVSEL#
PBDEVSEL#
I/O
Device Select: The Intel® 6700PXH 64-bit PCI Hub asserts PxDEVSEL# to
claim a PCI transaction. As a target, the Intel® 6700PXH 64-bit PCI Hub asserts
PxDEVSEL# when a PCI master peripheral attempts an access to an internal
address or an address destined for the PCI Express* interface. As an initiator,
PxDEVSEL# indicates the response to a Intel® 6700PXH 64-bit PCI Hub-initiated
transaction on the PCI bus. PxDEVSEL# is tri-stated from the leading edge of
PxPCIRST#. PxDEVSEL# remains tri-stated by the Intel® 6700PXH 64-bit PCI
Hub until driven as a target.
PAFRAME#
PBFRAME#
I/O
O
Frame: PxFRAME# is driven by the Initiator to indicate the beginning and
duration of an access. While PxFRAME# is asserted, data transfers continue.
When PxFRAME# is negated, the transaction is in the final data phase.
PAGNT_[5:0]#
PBGNT_[5:0]#
PCI Grants: Bus grant output corresponding to request inputs 5 through 0 from
the Intel® 6700PXH 64-bit PCI Hub arbiter. This signal indicates that an initiator
can start a transaction on the PCI bus.
PAIRDY#
PBIRDY#
I/O
I/O
Initiator Ready: PxIRDY# indicates the ability of the initiator to complete the
current data phase of the transaction. A data phase is completed when both
PxIRDY# and PxTRDY# are sampled asserted.
PAM66EN
PBM66EN
Only relevant when Hot Plug Mode is disabled (HPx_SLOT[3] = 0) or when in
one-slot-no-glue hot plug mode (HPx_SLOT[3:0] = 1111).
66 MHz Enable: This input signal from the PCI Bus indicates the speed of the
PCI Bus. If it is high, the bus speed is 66 MHz; if it is low, the bus speed is
33 MHz. This signal will be used to generate the appropriate clock (33 MHz or
66 MHz) on the PCI Bus.
Hot Plug Mode Enabled: Not used. The PCI bus will power up as 33 MHz PCI
and the Intel® 6700PXH 64-bit PCI Hub will drive this pin low. Also, if software
ever writes 00 to the PFREQ Register, the Intel® 6700PXH 64-bit PCI Hub will
drive this pin low.
Hot Plug Mode Disabled: Controls max frequency (33 MHz or 66 MHz) of the PCI
segment when running in conventional PCI mode:
0 = 33 MHz PCI
1 = 66 MHz PCI
PAPAR
PBPAR
I/O
Parity: Even parity calculated on 36 bits (PxAD[31:0] plus PxCBE_[3:0]#). It is
calculated on all 36 bits, regardless of the valid byte enables. It is driven
identically to the PxAD[31:0] lines, except it is delayed by exactly one PCI clock.
20
Intel® 6700PXH 64-bit PCI Hub Datasheet
INTEL [ INTEL ]
