Signal Description
Table 2-7. Parallel Mode Hot Plug Signals – Interface A and B – 1 to 2 Slots (Sheet 2 of 4)
Signal
Type
Description
HPA_SOL/
HABUTTON2#
O
Slot 2 Attention Button: Optional. Attention button input signal connected
to the second hot plug slot’s attention button. When low, indicates that the
operator has requested attention. If attention button is not implemented,
then this input must be wired to a high logic level. Only used when in dual-
slot parallel hot plug mode (HPx_SLOT[3:0] = 1010).
HPB_SOL/
HBBUTTON2#
HPA_SIL#/
HACLKEN_1#
O
O
I
Slot 1 Clock Enable: Clock enable signals that connect the PCI clock
signals of the first PCI slot to the system bus PCI bus via FET isolation
switches.
Only used when in single-slot or dual-slot parallel hot plug mode
(HPx_SLOT[3:0] = 1001 or 1010).
HPB_SIL#/
HBCLKEN_1#
HPA_SOD/
HACLKEN_2
Slot 2 Clock Enable: Clock enable signals that connect the PCI clock
signals of the second PCI slot to the system bus PCI bus via FET isolation
switches. Only used when in dual-slot parallel hot plug mode
(HPx_SLOT[3:0] = 1010).
HPB_SOD/
HBCLKEN_2
PAIRQ_[11]#/
HAM66EN_1
Slot 1 M66EN: Determines if an add-in card is capable of running at 66
MHz in conventional PCI mode for the first hot plug slot.
Only used when in one-slot-no-glue, single-slot parallel, or dual-slot parallel
hot plug mode (HPx_SLOT[3:0] = 1111, 1001, or 1010).
PBIRQ_[11]#/
HBM66EN_1
PAIRQ_[12]#/
HAM66EN_2
I
Slot 2 M66EN: Determines if an add-in card is capable of running at 66
MHz in conventional PCI mode for the second hot plug slot. Only used
when in dual-slot parallel hot plug mode (HPx_SLOT[3:0] = 1010).
PBIRQ_[12]#/
HBM66EN_2
PAIRQ_[15]#/
HAMRL1#
I
Slot 1 Manual Retention Latch: Optional. Manually operated retention
latch sensor input. A logic low input that is connected directly to the MRL
sensor on the first hot plug slot. When asserted it indicates that the MRL
latch is closed. If a platform does not support MRL sensors, this must be
wired to a low logic level (MRL closed).
PBIRQ_[15]#/
HBMRL1#
Only used when in one-slot-no-glue, single-slot parallel, or dual-slot parallel
hot plug mode (HPx_SLOT[3:0] = 1111, 1001, or 1010).
HPA_SLOT[0]/
HAMRL_2#
I
I
Slot 2 Manual Retention Latch: Optional. Manually operated retention
latch sensor input. A logic low input that is connected directly to the MRL
sensor on the second hot plug slot. When asserted it indicates that the MRL
latch is closed. If a platform does not support MRL sensors, this must be
wired to a low logic level (MRL closed). Only used when in dual-slot parallel
hot plug mode (HPx_SLOT[3:0] = 1010).
HPB_SLOT[0]/
HBMRL_2#
PAIRQ_[10]#/
Slot 1 PCIXCAP1: Determines if the first hot plug slot is PCI-X capable,
and if so, whether it can operate at 133 MHz. PCIXCAP1 and PCIXCAP2
represent a decoded version of the three-state PCIXCAP pin present on
each slot. PCIXCAP2 represents whether the PCIXCAP pin was ground or
not ground (i.e., PCI-X capable), and PCIXCAP1 represents whether the
PCIXCAP pin was “low” (66 MHz only) or high (133 MHz capable). The
system initially powers up at 33 MHz PCI, and all hot plug slots are scanned
by firmware. If the system is capable, the bus is reset to run in the
appropriate PCI-X mode. These pins are used only in one-slot-no-glue,
single-slot parallel or dual-slot parallel hot plug mode (HPx_SLOT[3:0] =
1111,1001 or 1010).
HAPCIXCAP1_1
PBIRQ_[10]#/
HBPCIXCAP1_1
Intel® 6700PXH 64-bit PCI Hub Datasheet
25
INTEL [ INTEL ]
