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Switching Characteristics
Table 28. Transceiver Specifications for Stratix V GT Devices (Part 5 of 5) (1)
Transceiver
Transceiver
Symbol/
Speed Grade 2
Speed Grade 3
Conditions
Unit
Max
Description
Min
Typ
Max
Min
Typ
(14)
tpll_lock
—
—
—
10
—
—
10
µs
Notes to Table 28:
(1) Speed grades shown refer to the PMA Speed Grade in the device ordering code. The maximum data rate could be restricted by the Core/PCS
speed grade. Contact your Altera Sales Representative for the maximum data rate specifications in each speed grade combination offered. For
more information about device ordering codes, refer to the Stratix V Device Overview.
(2) The reference clock common mode voltage is equal to the VCCR_GXB power supply level.
(3) The device cannot tolerate prolonged operation at this absolute maximum.
(4) The differential eye opening specification at the receiver input pins assumes that receiver equalization is disabled. If you enable receiver
equalization, the receiver circuitry can tolerate a lower minimum eye opening, depending on the equalization level.
(5) Refer to Figure 4 for the GT channel AC gain curves. The total effective AC gain is the AC gain minus the DC gain.
(6) Refer to Figure 5 for the GT channel DC gain curves.
(7) CFP2 optical modules require the host interface to have the receiver data pins differentially terminated with 100 . The internal OCT feature is
available after the Stratix V FPGA configuration is completed. Altera recommends that FPGA configuration is completed before inserting the
optical module. Otherwise, minimize unnecessary removal and insertion with unconfigured devices.
(8) Specifications for this parameter are the same as for Stratix V GX and GS devices. See Table 23 for specifications.
(9) tLTR is the time required for the receive CDR to lock to the input reference clock frequency after coming out of reset.
(10) tLTD is time required for the receiver CDR to start recovering valid data after the rx_is_lockedtodatasignal goes high.
(11) tLTD_manual is the time required for the receiver CDR to start recovering valid data after the rx_is_lockedtodatasignal goes high when the
CDR is functioning in the manual mode.
(12) tLTR_LTD_manual is the time the receiver CDR must be kept in lock to reference (LTR) mode after the rx_is_lockedtorefsignal goes high when
the CDR is functioning in the manual mode.
(13) tpll_powerdownis the PLL powerdown minimum pulse width.
(14) tpll_lockis the time required for the transmitter CMU/ATX PLL to lock to the input reference clock frequency after coming out of reset.
(15) To calculate the REFCLK rms phase jitter requirement for PCIe at reference clock frequencies other than 100 MHz, use the following formula:
REFCLK rms phase jitter at f(MHz) = REFCLK rms phase jitter at 100 MHz × 100/f.
(16) The maximum peak to peak differential input voltage VID after device configuration is equal to 4 × (absolute VMAX for receiver pin - VICM).
(17) For ES devices, RREF is 2000 1%.
(18) To calculate the REFCLK phase noise requirement at frequencies other than 622 MHz, use the following formula: REFCLK phase noise at f(MHz)
= REFCLK phase noise at 622 MHz + 20*log(f/622).
(19) SFP/+ optical modules require the host interface to have RD+/- differentially terminated with 100 . The internal OCT feature is available after
the Stratix V FPGA configuration is completed. Altera recommends that FPGA configuration is completed before inserting the optical module.
Otherwise, minimize unnecessary removal and insertion with unconfigured devices.
(20) Refer to Figure 3.
(21) For oversampling design to support data rates less than the minimum specification, the CDR needs to be in LTR mode only.
(22) This supply follows VCCR_GXB for both GX and GT channels.
(23) When you use fPLL as a TXPLL of the transceiver.
Stratix V Device Datasheet
December 2015 Altera Corporation
INTEL [ INTEL ]
