Page 16
Electrical Characteristics
Table 21. Differential HSTL and HSUL I/O Standards for Stratix V Devices (Part 2 of 2)
V
CCIO (V)
VDIF(DC) (V)
VX(AC) (V)
Typ
VCM(DC) (V)
VDIF(AC) (V)
I/O
Standard
Min
Typ
Max
Min
0.16
Max
Min
Max
Min
Typ
Max
Min
Max
HSTL-12
Class I, II
VCCIO
+ 0.3
0.5*
VCCIO
0.4*
VCCIO
0.5*
VCCIO
0.6*
VCCIO
VCCIO
+ 0.48
1.14
1.2
1.2
1.26
—
—
0.3
0.5*VCCIO 0.5* 0.5*VCCIO 0.4*
– 0.12 VCCIO + 0.12 VCCIO
0.5*
VCCIO
0.6*
VCCIO
HSUL-12
1.14
1.3
0.26 0.26
0.44
0.44
Table 22. Differential I/O Standard Specifications for Stratix V Devices (7)
(10)
(6)
(6)
V
CCIO (V)
VID (mV) (8)
VICM(DC) (V)
VOD (V)
VOCM (V)
Typ
I/O
Standard
Min Typ Max Min Condition Max Min Condition Max
Min Typ Max Min
Max
Transmitter, receiver, and input reference clock pins of the high-speed transceivers use the PCML I/O standard. For
transmitter, receiver, and reference clock I/O pin specifications, refer to Table 23 on page 18.
PCML
D
MAX
—
0.05
1.8 0.247
1.55 0.247
—
0.6 1.125 1.25 1.375
0.6 1.125 1.25 1.375
700 Mbps
2.5 V
LVDS
VCM
1.25 V
=
2.375 2.5 2.625 100
(1)
DMAX
700 Mbps
>
—
—
—
1.05
—
—
—
BLVDS (5) 2.375 2.5 2.625 100
RSDS
—
—
—
—
—
—
—
—
VCM
1.25 V
=
2.375 2.5 2.625 100
0.3
—
—
1.4
0.1
0.2 0.6
0.5
1.2
1.4
(2)
(HIO)
Mini-
LVDS
(HIO)
2.375 2.5 2.625 200
—
600 0.4
1.325 0.25
—
0.6
1
1.2
1.4
(3)
D
MAX
—
—
—
—
—
—
—
—
—
—
—
—
0.6
1
1.8
1.6
—
—
—
—
—
—
—
—
—
—
—
—
LVPECL (4
700 Mbps
), (9)
DMAX
700 Mbps
>
Notes to Table 22:
(1) For optimized LVDS receiver performance, the receiver voltage input range must be between 1.0 V to 1.6 V for data rates above 700 Mbps, and 0 V to 1.85
V for data rates below 700 Mbps.
(2) For optimized RSDS receiver performance, the receiver voltage input range must be between 0.25 V to 1.45 V.
(3) For optimized Mini-LVDS receiver performance, the receiver voltage input range must be between 0.3 V to 1.425 V.
(4) For optimized LVPECL receiver performance, the receiver voltage input range must be between 0.85 V to 1.75 V for data rate above 700 Mbps and 0.45 V
to 1.95 V for data rate below 700 Mbps.
(5) There are no fixed VICM, VOD, and VOCM specifications for BLVDS. They depend on the system topology.
(6) RL range: 90 RL 110 .
(7) The 1.4-V and 1.5-V PCML transceiver I/O standard specifications are described in “Transceiver Performance Specifications” on page 18.
(8) The minimum VID value is applicable over the entire common mode range, VCM.
(9) LVPECL is only supported on dedicated clock input pins.
(10) Differential inputs are powered by VCCPD which requires 2.5 V.
Power Consumption
Altera offers two ways to estimate power consumption for a design—the Excel-based
Early Power Estimator and the Quartus® II PowerPlay Power Analyzer feature.
Stratix V Device Datasheet
December 2015 Altera Corporation
INTEL [ INTEL ]
