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Switching Characteristics
Switching Characteristics
This section provides performance characteristics of the Stratix V core and periphery
blocks.
These characteristics can be designated as Preliminary or Final.
■
■
Preliminary characteristics are created using simulation results, process data, and
other known parameters. The title of these tables show the designation as
“Preliminary.”
Final numbers are based on actual silicon characterization and testing. The
numbers reflect the actual performance of the device under worst-case silicon
process, voltage, and junction temperature conditions. There are no designations
on finalized tables.
Transceiver Performance Specifications
This section describes transceiver performance specifications.
Table 23 lists the Stratix V GX and GS transceiver specifications.
(1)
Table 23. Transceiver Specifications for Stratix V GX and GS Devices
(Part 1 of 7)
Transceiver Speed
Grade 1
Transceiver Speed
Grade 2
Transceiver Speed
Grade 3
Symbol/
Description
Conditions
Unit
Min
Typ
Max
Min
Typ
Max
Min Typ
Max
Reference Clock
Dedicated
reference
clock pin
1.2-V PCML, 1.4-V PCML, 1.5-V PCML, 2.5-V PCML, Differential LVPECL, LVDS, and
HCSL
Supported I/O
Standards
RX reference
clock pin
1.4-V PCML, 1.5-V PCML, 2.5-V PCML, LVPECL, and LVDS
Input Reference
Clock Frequency
(CMU PLL) (8)
—
—
40
—
—
710
710
40
—
—
710
710
40
—
—
710
710
MHz
MHz
Input Reference
Clock Frequency
(ATX PLL) (8)
100
100
100
Measure at
60 mV of
differential
signal (26)
Rise time
—
—
—
—
400
400
—
—
—
—
400
400
—
—
—
—
400
400
ps
Measure at
60 mV of
differential
signal (26)
Fall time
Duty cycle
—
45
30
—
—
55
33
45
30
—
—
55
33
45
30
—
—
55
33
%
Spread-spectrum
modulating clock
frequency
PCI Express®
(PCIe®)
kHz
Stratix V Device Datasheet
December 2015 Altera Corporation
INTEL [ INTEL ]
