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5M160ZE64C4N 参数 Datasheet PDF下载

5M160ZE64C4N图片预览
型号: 5M160ZE64C4N
PDF下载: 下载PDF文件 查看货源
内容描述: [Flash PLD, 7.9ns, 128-Cell, CMOS, PQFP64, 9 X 9 MM, 0.40 MM PITCH, LEAD FREE, PLASTIC, EQFP-64]
分类和应用: 时钟可编程逻辑
文件页数/大小: 166 页 / 3966 K
品牌: INTEL [ INTEL ]
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3–26  
Chapter 3: DC and Switching Characteristics for MAX V Devices  
Timing Model and Specifications  
Maximum Input and Output Clock Rates  
Table 3–37 and Table 3–38 list the maximum input and output clock rates for standard  
I/O pins in MAX V devices.  
Table 3–37. Maximum Input Clock Rate for I/Os for MAX V Devices  
5M40Z/ 5M80Z/ 5M160Z/  
5M240Z/ 5M570Z/5M1270Z/  
I/O Standard  
Unit  
5M2210Z  
C4, C5, I5  
304  
Without Schmitt Trigger  
MHz  
MHz  
MHz  
MHz  
MHz  
MHz  
MHz  
MHz  
MHz  
MHz  
MHz  
MHz  
MHz  
3.3-V LVTTL  
With Schmitt Trigger  
304  
Without Schmitt Trigger  
With Schmitt Trigger  
304  
3.3-V LVCMOS  
2.5-V LVTTL  
304  
Without Schmitt Trigger  
With Schmitt Trigger  
304  
304  
Without Schmitt Trigger  
With Schmitt Trigger  
304  
2.5-V LVCMOS  
304  
1.8-V LVTTL  
1.8-V LVCMOS  
1.5-V LVCMOS  
1.2-V LVCMOS  
3.3-V PCI  
Without Schmitt Trigger  
Without Schmitt Trigger  
Without Schmitt Trigger  
Without Schmitt Trigger  
Without Schmitt Trigger  
200  
200  
150  
120  
304  
Table 3–38. Maximum Output Clock Rate for I/Os for MAX V Devices  
5M40Z/ 5M80Z/ 5M160Z/  
5M240Z/ 5M570Z/5M1270Z/  
5M2210Z  
I/O Standard  
Unit  
C4, C5, I5  
304  
3.3-V LVTTL  
3.3-V LVCMOS  
2.5-V LVTTL  
2.5-V LVCMOS  
1.8-V LVTTL  
1.8-V LVCMOS  
1.5-V LVCMOS  
1.2-V LVCMOS  
3.3-V PCI  
MHz  
MHz  
MHz  
MHz  
MHz  
MHz  
MHz  
MHz  
MHz  
MHz  
MHz  
304  
304  
304  
200  
200  
150  
120  
304  
LVDS  
304  
RSDS  
200  
MAX V Device Handbook  
May 2011 Altera Corporation  
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