3–24
Chapter 3: DC and Switching Characteristics for MAX V Devices
Timing Model and Specifications
Table 3–33. External Timing Input Delay tGLOB Adders for GCLK Pins for MAX V Devices (Part 2 of 2)
5M40Z/ 5M80Z/ 5M160Z/
5M1270Z/ 5M2210Z
5M240Z/ 5M570Z
I/O Standard
Unit
C4
C5, I5
C4
C5, I5
Min
Max
Min
Max
Min
Max
Min
Max
Without Schmitt
Trigger
—
0
—
0
—
0
—
0
ps
ps
ps
ps
ps
ps
ps
ps
3.3-V LVCMOS
With Schmitt
Trigger
—
—
—
—
—
—
—
387
242
429
378
681
1,055
0
—
—
—
—
—
—
—
442
242
483
368
658
—
—
—
—
—
—
—
400
287
550
459
1,111
2,067
7
—
—
—
—
—
—
—
493
353
677
565
Without Schmitt
Trigger
2.5-V LVTTL /
LVCMOS
With Schmitt
Trigger
1.8-V LVTTL / Without Schmitt
LVCMOS
Trigger
Without Schmitt
Trigger
1.5-V LVCMOS
1,368
2,544
9
Without Schmitt
Trigger
1.2-V LVCMOS
3.3-V PCI
1,010
0
Without Schmitt
Trigger
Table 3–34. External Timing Output Delay and tOD Adders for Fast Slew Rate for MAX V Devices
5M40Z/ 5M80Z/ 5M160Z/
5M1270Z/ 5M2210Z
C4 C5, I5
5M240Z/ 5M570Z
I/O Standard
Unit
C4
C5, I5
Min
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Max
0
Min
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Max
0
Min
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Max
0
Min
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Max
0
16 mA
8 mA
8 mA
4 mA
14 mA
7 mA
6 mA
3 mA
4 mA
2 mA
3 mA
20 mA
—
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
3.3-V LVTTL
39
58
84
104
0
0
0
0
3.3-V LVCMOS
39
58
84
104
195
309
909
122
196
624
686
1,188
1,279
1,911
39
129
188
624
694
158
251
738
850
1,376
1,517
2,206
4
2.5-V LVTTL / LVCMOS
1.8-V LVTTL / LVCMOS
1.5-V LVCMOS
1,046
1,694
1,867
2,715
5
1,184
1,280
1,883
58
1.2-V LVCMOS
3.3-V PCI
LVDS
122
122
129
158
158
195
RSDS
—
129
195
MAX V Device Handbook
May 2011 Altera Corporation
INTEL [ INTEL ]
