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5M160ZE64C4N 参数 Datasheet PDF下载

5M160ZE64C4N图片预览
型号: 5M160ZE64C4N
PDF下载: 下载PDF文件 查看货源
内容描述: [Flash PLD, 7.9ns, 128-Cell, CMOS, PQFP64, 9 X 9 MM, 0.40 MM PITCH, LEAD FREE, PLASTIC, EQFP-64]
分类和应用: 时钟可编程逻辑
文件页数/大小: 166 页 / 3966 K
品牌: INTEL [ INTEL ]
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3–22  
Chapter 3: DC and Switching Characteristics for MAX V Devices  
Timing Model and Specifications  
Table 3–30 lists the external I/O timing parameters for the F324 package of the  
5M1270Z device.  
Table 3–30. Global Clock External I/O Timing Parameters for the 5M1270Z Device (Note 1), (2)  
C4  
C5, I5  
Symbol  
tPD1  
Parameter  
Condition  
Unit  
Min  
Max  
9.1  
4.8  
Min  
Max  
11.2  
5.9  
Worst case pin-to-pin delay through one LUT  
Best case pin-to-pin delay through one LUT  
Global clock setup time  
10 pF  
10 pF  
ns  
ns  
ns  
ns  
ns  
ps  
ps  
tPD2  
tSU  
tH  
1.5  
0
1.9  
0
Global clock hold time  
tCO  
tCH  
tCL  
Global clock to output delay  
Global clock high time  
10 pF  
2.0  
216  
216  
6.0  
2.0  
266  
266  
7.4  
Global clock low time  
Minimum global clock period for 16-bit  
counter  
tCNT  
fCNT  
4.0  
5.0  
ns  
Maximum global clock frequency for 16-bit  
counter  
247.5  
201.1  
MHz  
Notes to Table 3–30:  
(1) The maximum frequency is limited by the I/O standard on the clock input pin. The 16-bit counter critical delay performs faster than this global  
clock input pin maximum frequency.  
(2) Only applicable to the F324 package of the 5M1270Z device.  
Table 3–31 lists the external I/O timing parameters for the 5M2210Z device.  
Table 3–31. Global Clock External I/O Timing Parameters for the 5M2210Z Device (Note 1)  
C4  
C5, I5  
Symbol  
tPD1  
Parameter  
Condition  
Unit  
Min  
Max  
9.1  
4.8  
Min  
Max  
11.2  
5.9  
Worst case pin-to-pin delay through one LUT  
Best case pin-to-pin delay through one LUT  
Global clock setup time  
10 pF  
10 pF  
ns  
ns  
ns  
ns  
ns  
ps  
ps  
tPD2  
tSU  
tH  
1.5  
0
1.9  
0
Global clock hold time  
tCO  
tCH  
tCL  
Global clock to output delay  
Global clock high time  
10 pF  
2.0  
216  
216  
6.0  
2.0  
266  
266  
7.4  
Global clock low time  
Minimum global clock period for 16-bit  
counter  
tCNT  
fCNT  
4.0  
5.0  
ns  
Maximum global clock frequency for 16-bit  
counter  
247.5  
201.1  
MHz  
Note to Table 3–31:  
(1) The maximum frequency is limited by the I/O standard on the clock input pin. The 16-bit counter critical delay performs faster than this global  
clock input pin maximum frequency.  
MAX V Device Handbook  
May 2011 Altera Corporation  
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