3–30
Chapter 3: DC and Switching Characteristics for MAX V Devices
Document Revision History
Table 3–41. JTAG Timing Parameters for MAX V Devices (Part 2 of 2)
Symbol
Parameter
Min
Max
Unit
tJSXZ
Notes to Table 3–41:
(1) Minimum clock period specified for 10 pF load on the TDOpin. Larger loads on TDOdegrades the maximum TCKfrequency.
Update register valid output to high impedance
—
25
ns
(2) This specification is shown for 3.3-V LVTTL/LVCMOS and 2.5-V LVTTL/LVCMOS operation of the JTAG pins. For 1.8-V LVTTL/LVCMOS and
1.5-V LVCMOS operation, the tJPSU minimum is 6 ns and tJPCO, tJPZX, and tJPXZ are maximum values at 35 ns.
Document Revision History
Table 3–42 lists the revision history for this chapter.
Table 3–42. Document Revision History
Date
May 2011
Version
1.2
Changes
Updated Table 3–2, Table 3–15, Table 3–16, and Table 3–33.
Updated Table 3–37, Table 3–38, Table 3–39, and Table 3–40.
Initial release.
January 2011
1.1
December 2010
1.0
MAX V Device Handbook
May 2011 Altera Corporation
INTEL [ INTEL ]
