Chapter 3: DC and Switching Characteristics for MAX V Devices
3–23
Timing Model and Specifications
External Timing I/O Delay Adders
The I/O delay timing parameters for the I/O standard input and output adders and
the input delays are specified by speed grade, independent of device density.
Table 3–32 through Table 3–36 on page 3–25 list the adder delays associated with I/O
pins for all packages. If you select an I/O standard other than 3.3-V LVTTL, add the
input delay adder to the external tSU timing parameters listed in Table 3–26 on
page 3–20 through Table 3–31. If you select an I/O standard other than 3.3-V LVTTL
with 16 mA drive strength and fast slew rate, add the output delay adder to the
external tCO and tPD listed in Table 3–26 on page 3–20 through Table 3–31.
Table 3–32. External Timing Input Delay Adders for MAX V Devices
5M40Z/ 5M80Z/ 5M160Z/
5M240Z/ 5M570Z
5M1270Z/ 5M2210Z
C4 C5, I5
I/O Standard
Unit
C4
C5, I5
Min
Max
Min
Max
Min
Max
Min
Max
Without Schmitt
Trigger
—
0
—
0
—
0
—
0
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
3.3-V LVTTL
With Schmitt
Trigger
—
—
—
—
—
—
—
—
—
387
0
—
—
—
—
—
—
—
—
—
442
0
—
—
—
—
—
—
—
—
—
480
0
—
—
—
—
—
—
—
—
—
591
0
Without Schmitt
Trigger
3.3-V LVCMOS
With Schmitt
Trigger
387
42
442
42
480
246
787
695
1,334
2,324
0
591
303
968
855
Without Schmitt
Trigger
2.5-V LVTTL /
LVCMOS
With Schmitt
Trigger
429
378
681
1,055
0
483
368
658
1.8-V LVTTL / Without Schmitt
LVCMOS
Trigger
Without Schmitt
Trigger
1.5-V LVCMOS
1,642
2,860
0
Without Schmitt
Trigger
1.2-V LVCMOS
3.3-V PCI
1,010
0
Without Schmitt
Trigger
Table 3–33. External Timing Input Delay tGLOB Adders for GCLK Pins for MAX V Devices (Part 1 of 2)
5M40Z/ 5M80Z/ 5M160Z/
5M1270Z/ 5M2210Z
5M240Z/ 5M570Z
I/O Standard
Unit
C4
C5, I5
C4
C5, I5
Min
Max
Min
Max
Min
Max
Min
Max
Without Schmitt
Trigger
—
0
—
0
—
0
—
0
ps
ps
3.3-V LVTTL
With Schmitt
Trigger
—
387
—
442
—
400
—
493
May 2011 Altera Corporation
MAX V Device Handbook
INTEL [ INTEL ]
