Page 54
Configuration Specification
Table 55 lists the PS timing parameter for Cyclone V devices.
Table 55. PS Timing Parameters for Cyclone V Devices
Symbol
tCF2CD
Parameter
nCONFIG low to CONF_DONE low
nCONFIG low to nSTATUS low
Minimum
Maximum
600
Unit
ns
—
—
tCF2ST0
600
ns
nCONFIG low pulse width
2
—
µs
µs
tCFG
(1)
nSTATUS low pulse width
268
1506
tSTATUS
tCF2ST1
(2)
nCONFIG high to nSTATUS high
nCONFIG high to first rising edge on DCLK
nSTATUS high to first rising edge of DCLK
DATA[] setup time before rising edge on DCLK
DATA[] hold time after rising edge on DCLK
DCLK high time
—
1506
µs
(3)
1506
—
—
µs
tCF2CK
(3)
2
µs
tST2CK
5.5
—
ns
tDSU
tDH
0
—
ns
0.45 x 1/fMAX
—
s
tCH
DCLK low time
0.45 x 1/fMAX
—
s
tCL
DCLK period
1/fMAX
—
s
tCLK
DCLK frequency
—
175
125
437
—
MHz
µs
fMAX
tCD2UM
tCD2CU
tCD2UMC
Tinit
CONF_DONE high to user mode (4)
CONF_DONE high to CLKUSR enabled
CONF_DONE high to user mode with CLKUSR option on
Number of clock cycles required for device initialization
4 x maximum DCLK period
—
—
Cycles
tCD2CU + (Tinit
x
CLKUSR period)
—
17,408
—
Notes to Table 55:
(1) You can obtain this value if you do not delay configuration by extending the nCONFIG or nSTATUS low pulse width.
(2) You can obtain this value if you do not delay configuration by externally holding nSTATUS low.
(3) If nSTATUS is monitored, follow the tST2CK specification. If nSTATUS is not monitored, follow the tCF2CK specification.
(4) The minimum and maximum numbers apply only if you chose the internal oscillator as the clock source for initializing the device.
Cyclone V Device Datasheet
July 2014 Altera Corporation
INTEL [ INTEL ]
