Configuration Specification
Page 51
Table 52 lists the timing parameters for Cyclone V devices when the
DCLK-to-DATA[]ratio is more than 1.
Table 52. DCLK-to-DATA[] FPP Timing Parameters for Cyclone V Devices when the Ratio is > 1 (1)
Symbol
tCF2CD
tCF2ST0
tCFG
tSTATUS
tCF2ST1
Parameter
nCONFIG low to CONF_DONE low
nCONFIG low to nSTATUS low
Minimum
Maximum
600
Unit
—
—
ns
ns
600
nCONFIG low pulse width
2
268
—
—
µs
µs
µs
µs
µs
(2)
nSTATUS low pulse width
1506
(3)
nCONFIG high to nSTATUS high
nCONFIG high to first rising edge on DCLK
nSTATUS high to first rising edge of DCLK
1506
(4)
1506
2
—
—
tCF2CK
tST2CK
tDSU
(4)
DATA[] setup time before rising edge on
DCLK
5.5
—
ns
(5)
DATA[] hold time after rising edge on DCLK
DCLK high time
N – 1/fDCLK
—
—
s
s
tDH
tCH
tCL
tCLK
fMAX
tR
0.45 x 1/fMAX
DCLK low time
0.45 x 1/fMAX
—
s
DCLK period
1/fMAX
—
s
DCLK frequency (FPP x8 and x16)
Input rise time
—
125
40
MHz
ns
ns
µs
—
—
Input fall time
—
175
40
tF
CONF_DONE high to user mode (6)
CONF_DONE high to CLKUSR enabled
437
—
tCD2UM
tCD2CU
4 × maximum DCLK period
t
CD2CU + (Tinit x CLKUSR
CONF_DONE high to user mode with CLKUSR
option on
tCD2UMC
—
—
—
period)
Number of clock cycles required for device
initialization
Tinit
17,408
Cycles
Notes to Table 52:
(1) Use these timing parameters when you use decompression and the design security features.
(2) This value can be obtained if you do not delay configuration by extending the nCONFIG or nSTATUS low pulse width.
(3) This value can be obtained if you do not delay configuration by externally holding nSTATUS low.
(4) If nSTATUS is monitored, follow the tST2CK specification. If nSTATUS is not monitored, follow the tCF2CK specification.
(5) N is the DCLK-to-DATA[] ratio and fDCLK is the DCLK frequency of the system.
(6) The minimum and maximum numbers apply only if you chose the internal oscillator as the clock source for initializing the device.
July 2014 Altera Corporation
Cyclone V Device Datasheet
INTEL [ INTEL ]
