Page 52
Configuration Specification
AS Configuration Timing
Figure 19 shows the timing waveform for the active serial (AS) x1 mode and AS x4
mode configuration timing.
Figure 19. AS Configuration Timing Waveform for Cyclone V Devices
t
CF2ST1
nCONFIG
nSTATUS
CONF_DONE
nCSO
DCLK
t
CO
t
DH
Read Address
AS_DATA0/ASDO
AS_DATA1 (1)
t
SU
bit (n − 2) bit (n − 1)
bit 1
bit 0
t
(2)
CD2UM
INIT_DONE (3)
User I/O
User Mode
Notes to Figure 19:
(1) If you are using AS x4 mode, this signal represents the AS_DATA[3..0] and EPCQ sends in 4-bits of data for each DCLK cycle.
(2) The initialization clock can be from the internal oscillator or the CLKUSR pin.
(3) After the option bit to enable the INIT_DONE pin is configured into the device, INIT_DONE goes low.
Table 53 lists the timing parameters for AS x1 and AS x4 configurations in Cyclone V
devices.
The minimum and maximum numbers apply to both the internal oscillator and
CLKUSR when either one is used as the clock source for device configuration.
The tCF2CD, tCF2ST0, tCFG, tSTATUS, and tCF2ST1 timing parameters are identical to the
timing parameters for passive serial (PS) mode listed in Table 55 on page 1–54. You
can obtain the tCF2ST1 value if you do not delay configuration by externally holding
nSTATUS low.
Table 53. AS Timing Parameters for AS x1 and x4 Configurations in Cyclone V Devices
Symbol
tCO
Parameter
Minimum
Maximum
Unit
ns
DCLK falling edge to the AS_DATA0
/ASDO output
—
4
tSU
Data setup time before the falling edge on DCLK
Data hold time after the falling edge on DCLK
CONF_DONE high to user mode
1.5
—
—
437
—
ns
tDH
0
175
ns
tCD2UM
tCD2CU
tCD2UMC
µs
CONF_DONE high to CLKUSR enabled
4 x maximum DCLK period
—
t
CD2CU + (Tinit x CLKUSR
CONF_DONE high to user mode with CLKUSR option on
—
—
—
period)
17,408
Number of clock cycles required for device initialization
Cycles
Tinit
Cyclone V Device Datasheet
July 2014 Altera Corporation
INTEL [ INTEL ]
