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I/O Timing
I/O Timing
Altera offers two ways to determine I/O timing—the Excel-based I/O Timing and the
Quartus II Timing Analyzer.
Excel-based I/O timing provides pin timing performance for each device density and
speed grade. The data is typically used prior to designing the FPGA to get an estimate
of the timing budget as part of the link timing analysis.
The Quartus II Timing Analyzer provides a more accurate and precise I/O timing
data based on the specifics of the design after you complete place-and-route.
f
You can download the Excel-based I/O Timing spreadsheet from the Cyclone V
Devices Documentation webpage.
Programmable IOE Delay
Table 61 lists the Cyclone V IOE programmable delay settings.
Table 61. IOE Programmable Delay for Cyclone V Devices
Fast Model
Slow Model
Parameter Available Minimum
Unit
(1)
Settings
Offset (2)
Industrial Commercial
–C6
–C7
–C8
–I7
–A7
D1
D3
D4
D5
32
8
0
0
0
0
0.508
1.761
0.510
0.508
0.517
1.793
0.519
0.517
0.971
3.291
1.180
0.970
1.187
4.022
1.187
1.186
1.194
3.961
1.195
1.194
1.179
3.999
1.180
1.179
1.160
3.929
1.160
1.179
ns
ns
ns
ns
32
32
Notes to Table 61:
(1) You can set this value in the Quartus II software by selecting D1, D3, D4, and D5 in the Assignment Name column of Assignment Editor.
(2) Minimum offset does not include the intrinsic delay.
Programmable Output Buffer Delay
Table 62 lists the delay chain settings that control the rising and falling edge delays of
the output buffer. The default delay is 0 ps.
You can set the programmable output buffer delay in the Quartus II software by
setting the Output Buffer Delay Control assignment to either positive, negative, or
both edges, with the specific values stated here (in ps) for the Output Buffer Delay
assignment.
Table 62. Programmable Output Buffer Delay for Cyclone V Devices
Symbol
Parameter
Typical
0 (default)
50
Unit
ps
ps
Rising and/or falling edge
delay
DOUTBUF
100
ps
150
ps
Cyclone V Device Datasheet
July 2014 Altera Corporation
INTEL [ INTEL ]
