Configuration Specification
Page 57
Table 58. Minimum Configuration Time Estimation for Cyclone V Devices (Part 2 of 2)
Active Serial (1)
Fast Passive Parallel (2)
Minimum
Configuration
Time (ms)
Minimum
Configuration Time
Variant
Member Code
DCLK
(MHz)
DCLK
(MHz)
Width
Width
(ms)
C2
C4
C5
C6
D5
D6
4
4
4
4
4
4
100
100
100
100
100
100
85
85
16
16
16
16
16
16
125
125
125
125
125
125
17
17
Cyclone V SX
140
140
140
140
28
28
28
Cyclone V ST
28
Notes to Table 57:
(1) DCLK frequency of 100 MHz using external CLKUSR
.
(2) Maximum FPGA FPP bandwidth may exceed bandwidth available from some external storage or control logic.
Remote System Upgrades Circuitry Timing Specification
Table 59 lists the timing parameter specifications for the remote system upgrade
circuitry.
Table 59. Remote System Upgrade Circuitry Timing Specification for Cyclone V Devices
Parameter
Minimum
250
Maximum
Unit
ns
(1)
tRU_nCONFIG
—
—
(2)
tRU_nRSTIMER
250
ns
Notes to Table 59:
(1) This is equivalent to strobing the reconfiguration input of the ALTREMOTE_UPDATE IP core high for the minimum
timing specification. For more information, refer to the “Remote System Upgrade State Machine” section in the
Configuration, Design Security, and Remote System Upgrades in Cyclone V Devices chapter.
(2) This is equivalent to strobing the reset timer input of the ALTREMOTE_UPDATE IP core high for the minimum
timing specification. For more information, refer to the “User Watchdog Timer” section in the Configuration,
Design Security, and Remote System Upgrades in Cyclone V Devices chapter.
User Watchdog Internal Oscillator Frequency Specification
Table 60 lists the frequency specifications for the user watchdog internal oscillator.
Table 60. User Watchdog Internal Oscillator Frequency Specifications for Cyclone V Devices
Parameter
Minimum
Typical
Maximum
Unit
User watchdog internal
oscillator frequency
5.3
7.9
12.5
MHz
July 2014 Altera Corporation
Cyclone V Device Datasheet
INTEL [ INTEL ]
