Configuration Specification
Page 53
Table 54 lists the internal clock frequency specification for the AS configuration
scheme.
The DCLK frequency specification applies when you use the internal oscillator as the
configuration clock source.
The AS multi-device configuration scheme does not support DCLK frequency of
100 MHz.
Table 54. DCLK Frequency Specification in the AS Configuration Scheme for Cyclone V Devices
Parameter
Minimum
5.3
Typical
7.9
Maximum
12.5
Unit
MHz
MHz
MHz
MHz
10.6
15.7
31.4
62.9
25.0
DCLK frequency in AS
configuration scheme
21.3
50.0
42.6
100.0
PS Configuration Timing
Figure 20 shows the timing waveform for a PS configuration when using a MAX II
device or microprocessor as an external host.
Figure 20. PS Configuration Timing Waveform for Cyclone V Devices (1)
tCF2ST1
tCFG
tCF2CK
nCONFIG
nSTATUS (2)
tSTATUS
tCF2ST0
(5)
t CLK
CONF_DONE (3)
tCH
tCL
tCF2CD
tST2CK
(4)
DCLK
tDH
Bit 2 Bit 3
Bit (n-1)
Bit 0 Bit 1
DATA0
tDSU
High-Z
User I/O
User Mod
INIT_DONE (6)
tCD2UM
Notes to Figure 20:
(1) The beginning of this waveform shows the device in user mode. In user mode, nCONFIG
nCONFIG is pulled low, a reconfiguration cycle begins.
, nSTATUS, and CONF_DONE are at logic high levels. When
(2) After power up, the Cyclone V device holds nSTATUS low for the time of the POR delay.
(3) After power up, before and during configuration, CONF_DONE is low.
(4) Do not leave DCLK floating after configuration. DCLK is ignored after configuration is complete. It can toggle high or low if required.
(5) To ensure a successful configuration, send the entire configuration data to the Cyclone V device. CONF_DONE is released high after the Cyclone V
device receives all the configuration data successfully. After CONF_DONE goes high, send two additional falling edges on DCLK to begin
initialization and enter user mode.
(6) After the option bit to enable the INIT_DONE pin is configured into the device, INIT_DONE goes low.
July 2014 Altera Corporation
Cyclone V Device Datasheet
INTEL [ INTEL ]
