Configuration Specification
Page 49
Table 51 lists the timing parameters for Cyclone V devices for an FPP configuration
when the DCLK-to-DATA[] ratio is 1.
Table 51. DCLK-to-DATA[] FPP Timing Parameters for Cyclone V Devices When the Ratio is 1
Symbol
tCF2CD
tCF2ST0
tCFG
tSTATUS
tCF2ST1
Parameter
nCONFIG low to CONF_DONE low
nCONFIG low to nSTATUS low
Minimum
Maximum
600
Unit
ns
—
—
600
ns
nCONFIG low pulse width
2
268
—
—
µs
µs
µs
µs
µs
(1)
nSTATUS low pulse width
1506
(2)
nCONFIG high to nSTATUS high
nCONFIG high to first rising edge on DCLK
nSTATUS high to first rising edge of DCLK
1506
(3)
1506
2
—
—
tCF2CK
tST2CK
tDSU
(3)
DATA[] setup time before rising edge on
DCLK
5.5
—
ns
DATA[] hold time after rising edge on DCLK
DCLK high time
0
—
—
ns
s
tDH
0.45 x 1/fMAX
tCH
DCLK low time
0.45 x 1/fMAX
—
s
tCL
DCLK period
1/fMAX
—
s
tCLK
fMAX
tCD2UM
tCD2CU
DCLK frequency (FPP x8 and x16)
—
175
125
437
—
MHz
µs
—
(4)
CONF_DONE high to user mode
CONF_DONE high to CLKUSR enabled
4 × maximum DCLK period
t
CD2CU + (Tinit x CLKUSR
CONF_DONE high to user mode with CLKUSR
option on
tCD2UMC
—
—
—
period)
Number of clock cycles required for device
initialization
Tinit
17,408
Cycles
Notes to Table 51:
(1) You can obtain this value if you do not delay configuration by extending the nCONFIG or nSTATUS low pulse width.
(2) You can obtain this value if you do not delay configuration by externally holding nSTATUS low.
(3) If nSTATUS is monitored, follow the tST2CK specification. If nSTATUS is not monitored, follow the tCF2CK specification.
(4) The minimum and maximum numbers apply only if you chose the internal oscillator as the clock source for initializing the device.
July 2014 Altera Corporation
Cyclone V Device Datasheet
INTEL [ INTEL ]
