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5CSEMA5F31C8N 参数 Datasheet PDF下载

5CSEMA5F31C8N图片预览
型号: 5CSEMA5F31C8N
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 85000-Cell, CMOS, PBGA896, ROHS COMPLIANT, FBGA-896]
分类和应用: 可编程逻辑
文件页数/大小: 93 页 / 999 K
品牌: INTEL [ INTEL ]
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Cyclone V Device Datasheet  
CV-51002 | 2018.05.07  
Exceptions for PCIe Gen2 design:  
VOD setting = 50 and pre-emphasis setting = 22 are allowed for PCIe Gen2 design with transmit de-emphasis –6dB  
setting (pipe_txdeemp = 1’b0) using Intel PCIe Hard IP and PIPE IP cores.  
VOD setting = 50 and pre-emphasis setting = 12 are allowed for PCIe Gen2 design with transmit de-emphasis –3.5dB  
setting (pipe_txdeemp = 1’b1) using Intel PCIe Hard IP and PIPE IP cores.  
For example, when VOD = 800 mV, the corresponding VOD value setting is 40. The following conditions show that the 1st post  
tap pre-emphasis setting = 2 is valid:  
|B| + |C| ≤ 6040 + 2 = 42  
|B| – |C| > 540 – 2 = 38  
(VMAX/VMIN – 1)% < 600%(42/38 – 1)% = 10.52%  
To predict the pre-emphasis level for your specific data rate and pattern, run simulations using the Cyclone V HSSI HSPICE  
models.  
Table 28.  
Transmitter Pre-Emphasis Levels for Cyclone V Devices  
Intel Quartus Prime 1st  
Intel Quartus Prime VOD Setting  
Unit  
Post Tap Pre-Emphasis  
Setting  
10 (200 mV)  
20 (400 mV)  
0
30 (600 mV)  
35 (700 mV)  
40 (800 mV)  
45 (900 mV)  
0
50 (1000 mV)  
0
0
1
0
1.97  
3.58  
5.35  
7.27  
0
0
0
dB  
dB  
dB  
dB  
dB  
dB  
dB  
dB  
dB  
dB  
0.88  
0.43  
0.95  
1.49  
2
0.32  
0.76  
1.2  
0.24  
0.61  
1
0.19  
0.5  
0.13  
2
1.67  
0.41  
3
2.48  
0.83  
1.14  
1.49  
1.83  
2.18  
2.48  
2.87  
3.23  
0.69  
4
3.31  
1.63  
2.1  
1.36  
1.76  
2.17  
2.58  
2.93  
3.38  
3.79  
0.96  
5
4.19  
2.55  
3.11  
3.71  
4.22  
4.86  
5.46  
1.26  
6
5.08  
2.56  
3.06  
3.47  
4
1.56  
7
5.99  
1.87  
8
6.92  
2.11  
9
7.92  
2.46  
10  
9.04  
4.51  
2.77  
dB  
continued...  
Cyclone V Device Datasheet  
36  
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