AV-51002
2015.12.16
1-94
Document Revision History
Date
Version
Changes
June 2015
2015.06.16
• Added the supported data rates for the following output standards using true LVDS output buffer types in
the High-Speed I/O Specifications for Arria V Devices table:
• True RSDS output standard: data rates of up to 360 Mbps
• True mini-LVDS output standard: data rates of up to 400 Mbps
• Added note in the condition for Transmitter—Emulated Differential I/O Standards fHSDR data rate
parameter in the High-Speed I/O Specifications for Arria V Devices table. Note: When using True LVDS RX
channels for emulated LVDS TX channel, only serialization factors 1 and 2 are supported.
• Changed Queued Serial Peripheral Interface (QSPI) to Quad Serial Peripheral Interface (SPI) Flash.
• Updated Th location in I2C Timing Diagram.
• Updared Twp location in NAND Address Latch Timing Diagram.
• Corrected the unit for tDH from ns to s in FPP Timing Parameters When DCLK-to-DATA[] Ratio is >1 for
Arria V Devices table.
• Updated the maximum value for tCO from 4 ns to 2 ns in AS Timing Parameters for AS ×1 and ×4 Configu‐
rations in Arria V Devices table.
• Moved the following timing diagrams to the Configuration, Design Security, and Remote System Upgrades
in Arria V Devices chapter.
• FPP Configuration Timing Waveform When DCLK-to-DATA[] Ratio is 1
• FPP Configuration Timing Waveform When DCLK-to-DATA[] Ratio is >1
• AS Configuration Timing Waveform
• PS Configuration Timing Waveform
Arria V GX, GT, SX, and ST Device Datasheet
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