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5AGXMA1D6F27C6N 参数 Datasheet PDF下载

5AGXMA1D6F27C6N图片预览
型号: 5AGXMA1D6F27C6N
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 500MHz, 75000-Cell, CMOS, PBGA672, ROHS COMPLIANT, FBGA-672]
分类和应用: 可编程逻辑
文件页数/大小: 182 页 / 2239 K
品牌: INTEL [ INTEL ]
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AV-51002  
2015.12.16  
1-98  
Document Revision History  
Date  
Version  
Changes  
November 2012  
3.0  
• Updated Table 2, Table 4, Table 9, Table 14, Table 16, Table 17, Table 20, Table 21, Table 25, Table 29, Table  
36, Table 56, Table 57, and Table 60.  
• Removed table: Transceiver Block Jitter Specifications for Arria V Devices.  
• Added HPS information:  
• Added “HPS Specifications” section.  
• Added Table 38, Table 39, Table 40, Table 41, Table 42, Table 43, Table 44, Table 45, Table 46, Table 47,  
Table 48, Table 49, and Table 50.  
• Added Figure 7, Figure 8, Figure 9, Figure 10, Figure 11, Figure 12, Figure 13, Figure 14, Figure 15, Figure  
16, Figure 17, Figure 18, and Figure 19.  
• Updated Table 3 and Table 5.  
October 2012  
2.4  
• Updated Arria V GX VCCR_GXBL/R, VCCT_GXBL/R, and VCCL_GXBL/R minimum and maximum values, and  
data rate in Table 4.  
• Added receiver VICM (AC coupled) and VICM (DC coupled) values, and transmitter VOCM (AC coupled) and  
VOCM (DC coupled) values in Table 20 and Table 21.  
August 2012  
July 2012  
2.3  
2.2  
Updated the SERDES factor condition in Table 30.  
• Updated the maximum voltage for VI (DC input voltage) in Table 1.  
• Updated Table 20 to include the Arria V GX -I3 speed grade.  
• Updated the minimum value of the fixedclk clock frequency in Table 20 and Table 21.  
• Updated the SERDES factor condition in Table 30.  
• Updated Table 50 to include the IOE programmable delay settings for the Arria V GX -I3 speed grade.  
June 2012  
2.1  
Updated VCCR_GXBL/R, VCCT_GXBL/R, and VCCL_GXBL/R values in Table 4.  
Arria V GX, GT, SX, and ST Device Datasheet  
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Altera Corporation  
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