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5AGXMA1D6F27C6N 参数 Datasheet PDF下载

5AGXMA1D6F27C6N图片预览
型号: 5AGXMA1D6F27C6N
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 500MHz, 75000-Cell, CMOS, PBGA672, ROHS COMPLIANT, FBGA-672]
分类和应用: 可编程逻辑
文件页数/大小: 182 页 / 2239 K
品牌: INTEL [ INTEL ]
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AV-51002  
2015.12.16  
1-95  
Document Revision History  
Date  
Version  
Changes  
January 2015  
2015.01.30  
• Updated the description for VCC_AUX_SHARED to “HPS auxiliary power supply” in the following tables:  
• Absolute Maximum Ratings for Arria V Devices  
• HPS Power Supply Operating Conditions for Arria V SX and ST Devices  
• Added statement in I/O Standard Specifications: You must perform timing closure analysis to determine the  
maximum achievable frequency for general purpose I/O standards.  
• Updated the conditions for transceiver reference clock rise time and fall time: Measure at 60 mV of  
differential signal. Added a note to the conditions: REFCLKperformance requires to meet transmitter REFCLK  
phase noise specification.  
• Updated the description in Periphery Performance Specifications to mention that proper timing closure is  
required in design.  
• Updated HPS Clock Performance main_base_clk specifications from 525 MHz (for –I3 speed grade) and  
462 MHz (for –C4 speed grade) to 400 MHz.  
• Updated HPS PLL VCO maximum frequency to 1,600 MHz (for –C5, –I5, and –C6 speed grades), 1,850  
MHz (for –C4 speed grade), and 2,100 MHz (for –I3 speed grade).  
• Changed the symbol for HPS PLL input jitter divide value from NR to N.  
• Removed “Slave select pulse width (Texas Instruments SSP mode)” parameter from the following tables:  
• SPI Master Timing Requirements for Arria V Devices  
• SPI Slave Timing Requirements for Arria V Devices  
• Added descriptions to USB Timing Characteristics section in HPS Specifications: PHYs that support LPM  
mode may not function properly with the USB controller due to a timing issue. It is recommended that  
designers use the MicroChip USB3300 PHY device that has been proven to be successful on the develop‐  
ment board.  
• Added HPS JTAG timing specifications.  
• Updated FPGA JTAG timing specifications note as follows: A 1-ns adder is required for each VCCIO voltage  
step down from 3.0 V. For example, tJPCO = 13 ns if VCCIO of the TDO I/O bank = 2.5 V, or 14 ns if it equals  
1.8 V.  
• Updated the value in the VICM (AC Coupled) row and in note 6 from 650 mV to 750 mV in the Transceiver  
Specifications for Arria V GT and ST Devices table.  
Arria V GX, GT, SX, and ST Device Datasheet  
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Altera Corporation  
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