AV-51002
2015.12.16
1-90
Glossary
Term
Definition
PLL specifications
Diagram of PLL specifications
CLKOUT Pins
fOUT
Switchover
_EXT
4
CLK
fIN
fINPFD
N
GCLK
RCLK
Counters
C0..C17
fVCO
VCO
fOUT
PFD
CP
LF
Core Clock
Delta Sigma
Modulator
Legend
Reconfigurable in User Mode
External Feedback
Note:
(1) Core Clock can only be fed by dedicated clock input pins or PLL outputs.
RL
Receiver differential input discrete resistor (external to the Arria V device).
Sampling window (SW)
Timing diagram—The period of time during which the data must be valid in order to capture it correctly.
The setup and hold times determine the ideal strobe position in the sampling window, as shown:
Bit Time
Sampling Window
(SW)
RSKM
RSKM
0.5 x TCCS
0.5 x TCCS
Arria V GX, GT, SX, and ST Device Datasheet
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Altera Corporation
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