欢迎访问ic37.com |
会员登录 免费注册
发布采购

5AGXMA1D6F27C6N 参数 Datasheet PDF下载

5AGXMA1D6F27C6N图片预览
型号: 5AGXMA1D6F27C6N
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 500MHz, 75000-Cell, CMOS, PBGA672, ROHS COMPLIANT, FBGA-672]
分类和应用: 可编程逻辑
文件页数/大小: 182 页 / 2239 K
品牌: INTEL [ INTEL ]
 浏览型号5AGXMA1D6F27C6N的Datasheet PDF文件第95页浏览型号5AGXMA1D6F27C6N的Datasheet PDF文件第96页浏览型号5AGXMA1D6F27C6N的Datasheet PDF文件第97页浏览型号5AGXMA1D6F27C6N的Datasheet PDF文件第98页浏览型号5AGXMA1D6F27C6N的Datasheet PDF文件第100页浏览型号5AGXMA1D6F27C6N的Datasheet PDF文件第101页浏览型号5AGXMA1D6F27C6N的Datasheet PDF文件第102页浏览型号5AGXMA1D6F27C6N的Datasheet PDF文件第103页  
AV-51002  
2015.12.16  
1-96  
Document Revision History  
Date  
Version  
Changes  
July 2014  
3.8  
• Added a note in Table 3, Table 4, and Table 5: The power supply value describes the budget for the DC  
(static) power supply tolerance and does not include the dynamic tolerance requirements. Refer to the PDN  
tool for the additional budget for the dynamic tolerance requirements.  
• Updated VCC_HPS specification in Table 5.  
• Added a note in Table 19: Differential inputs are powered by VCCPD which requires 2.5 V.  
• Updated "Minimum differential eye opening at the receiver serial input pins" specification in Table 20 and  
Table 21.  
• Updated description in “HPS PLL Specifications” section.  
• Updated VCO range maximum specification in Table 39.  
• Updated Td and Th specifications in Table 45.  
• Added Th specification in Table 47 and Figure 13.  
• Updated a note in Figure 20, Figure 21, and Figure 23 as follows: Do not leave DCLK floating after configu‐  
ration. DCLK is ignored after configuration is complete. It can toggle high or low if required.  
• Removed “Remote update only in AS mode” specification in Table 58.  
• Added DCLK device initialization clock source specification in Table 60.  
• Added description in “Configuration Files” section: The IOCSR .rbf size is specifically for the Configuration  
via Protocol (CvP) feature.  
• Removed fMAX_RU_CLK specification in Table 63.  
February 2014  
December 2013  
3.7  
3.6  
• Updated VCCRSTCLK_HPS maximum specification in Table 1.  
• Added VCC_AUX_SHARED specification in Table 1.  
• Added “HPS PLL Specifications”.  
• Added Table 24, Table 39, and Table 40.  
• Updated Table 1, Table 3, Table 5, Table 19, Table 20, Table 21, Table 38, Table 41, Table 42, Table 43, Table  
44, Table 45, Table 46, Table 47, Table 48, Table 49, Table 50, Table 51, Table 55, Table 56, and Table 59.  
• Updated Figure 7, Figure 13, Figure 15, Figure 16, and Figure 19.  
• Removed table: GPIO Pulse Width for Arria V Devices.  
Arria V GX, GT, SX, and ST Device Datasheet  
Send Feedback  
Altera Corporation  
 复制成功!