AV-51002
2015.12.16
1-67
Ethernet Media Access Controller (EMAC) Timing Characteristics
Figure 1-13: RGMII TX Timing Diagram
TX_CLK
TX_D[3:0]
Td
TX_CTL
Table 1-57: RGMII RX Timing Requirements for Arria V Devices
Symbol
Tclk (1000Base-T)
Tclk (100Base-T)
Tclk (10Base-T)
Tsu
Description
Min
—
—
—
1
Typ
8
Unit
ns
RX_CLK clock period
RX_CLK clock period
RX_CLK clock period
RX_D/RX_CTL setup time
RX_D/RX_CTL hold time
40
400
—
ns
ns
ns
Th
1
—
ns
Figure 1-14: RGMII RX Timing Diagram
RX_CLK
Th
Tsu
RX_D[3:0]
RX_CTL
Table 1-58: Management Data Input/Output (MDIO) Timing Requirements for Arria V Devices
Symbol
Description
Min
—
Typ
400
—
Unit
ns
Tclk
Td
MDC clock period
MDC to MDIO output data delay
10
ns
Arria V GX, GT, SX, and ST Device Datasheet
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