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5AGXMA1D6F27C6N 参数 Datasheet PDF下载

5AGXMA1D6F27C6N图片预览
型号: 5AGXMA1D6F27C6N
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 500MHz, 75000-Cell, CMOS, PBGA672, ROHS COMPLIANT, FBGA-672]
分类和应用: 可编程逻辑
文件页数/大小: 182 页 / 2239 K
品牌: INTEL [ INTEL ]
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AV-51002  
2015.12.16  
1-28  
Transceiver Specifications for Arria V GX and SX Devices  
Transceiver Speed Grade 4  
Transceiver Speed Grade 6  
Symbol/Description  
Condition  
Unit  
Min  
Typ  
Max  
Min  
Typ  
Max  
Inter-transceiver block  
transmitter channel-to-  
channel skew(39)  
×N PMA bonded mode  
500  
500  
ps  
Table 1-24: CMU PLL Specifications for Arria V GX and SX Devices  
Transceiver Speed Grade 4  
Transceiver Speed Grade 6  
Symbol/Description  
Unit  
Min  
611  
611  
Max  
6553.6  
3125  
Min  
611  
611  
Max  
3125  
3125  
Supported data range  
fPLL supported data range  
Mbps  
Mbps  
Table 1-25: Transceiver-FPGA Fabric Interface Specifications for Arria V GX and SX Devices  
Transceiver Speed Grade 4 and 6  
Symbol/Description  
Unit  
Min  
25  
Max  
187.5  
163.84  
Interface speed (single-width mode)  
Interface speed (double-width mode)  
MHz  
MHz  
25  
Related Information  
CTLE Response at Data Rates > 3.25 Gbps across Supported AC Gain and DC Gain on page 1-35  
CTLE Response at Data Rates ≤ 3.25 Gbps across Supported AC Gain and DC Gain on page 1-36  
Arria V GT, GX, ST, and SX Device Family Pin Connection Guidelines  
Provides more information about the power supply connection for different data rates.  
(39)  
This specification is only applicable to channels on one side of the device across two transceiver banks.  
Arria V GX, GT, SX, and ST Device Datasheet  
Send Feedback  
Altera Corporation  
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