AV-51002
2015.12.16
1-31
Transceiver Specifications for Arria V GT and ST Devices
Transceiver Speed Grade 3
Symbol/Description
Condition
Unit
Min
—
Typ
—
Max
1.2
—
Absolute VMAX for a receiver pin(45)
Absolute VMIN for a receiver pin
—
—
—
V
V
V
–0.4
—
—
Maximum peak-to-peak differential
input voltage VID (diff p-p) before
device configuration
—
1.6
Maximum peak-to-peak differential
input voltage VID (diff p-p) after
device configuration
—
—
—
—
—
2.2
—
V
Minimum differential eye opening
at the receiver serial input pins(46)
100
mV
VICM (AC coupled)
VICM (DC coupled)
—
—
750(47)/800
—
mV
mV
Ω
≤ 3.2Gbps(48)
85-Ω setting
100-Ω setting
120-Ω setting
150-Ω setting
—
670
700
85
730
100
120
150
—
Ω
Differential on-chip termination
resistors
Ω
Ω
(49)
tLTR
—
4
10
—
—
µs
(50)
tLTD
—
—
µs
(51)
tLTD_manual
—
4
—
µs
(45)
The device cannot tolerate prolonged operation at this absolute maximum.
(46)
The differential eye opening specification at the receiver input pins assumes that you have disabled the Receiver Equalization feature. If you enable
the Receiver Equalization feature, the receiver circuitry can tolerate a lower minimum eye opening, depending on the equalization level.
The AC coupled VICM is 750 mV for PCIe mode only.
(47)
(48)
(49)
(50)
For standard protocol compliance, use AC coupling.
tLTR is the time required for the receive CDR to lock to the input reference clock frequency after coming out of reset.
tLTD is time required for the receiver CDR to start recovering valid data after the rx_is_lockedtodatasignal goes high.
Arria V GX, GT, SX, and ST Device Datasheet
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