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5AGXMA1D6F27C6N 参数 Datasheet PDF下载

5AGXMA1D6F27C6N图片预览
型号: 5AGXMA1D6F27C6N
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 500MHz, 75000-Cell, CMOS, PBGA672, ROHS COMPLIANT, FBGA-672]
分类和应用: 可编程逻辑
文件页数/大小: 182 页 / 2239 K
品牌: INTEL [ INTEL ]
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AV-51002  
2015.12.16  
1-32  
Transceiver Specifications for Arria V GT and ST Devices  
Transceiver Speed Grade 3  
Symbol/Description  
Condition  
Unit  
Min  
Typ  
Max  
(52)  
tLTR_LTD_manual  
15  
µs  
ppm  
UI  
Programmable ppm detector(53)  
62.5, 100, 125, 200, 250, 300, 500, and 1000  
200  
Run length  
AC gain setting = 0 to 3(54)  
DC gain setting = 0 to 1  
Programmable equalization AC and  
DC gain  
Refer to CTLE Response at Data Rates > 3.25 Gbps across Supported AC Gain  
and DC Gain for Arria V GX, GT, SX, and ST Devices and CTLE Response at  
Data Rates ≤ 3.25 Gbps across Supported AC Gain and DC Gain for Arria V  
GX, GT, SX, and ST Devices diagrams.  
Table 1-29: Transmitter Specifications for Arria V GT and ST Devices  
Transceiver Speed Grade 3  
Unit  
Symbol/Description  
Condition  
Min  
Typ  
Max  
Supported I/O standards  
Data rate (6-Gbps transceiver)  
Data rate (10-Gbps transceiver)  
VOCM (AC coupled)  
1.5 V PCML  
611  
0.611  
6553.6  
10.3125  
Mbps  
Gbps  
mV  
650  
700  
VOCM (DC coupled)  
≤ 3.2 Gbps(48)  
670  
730  
mV  
(51)  
(52)  
tLTD_manual is the time required for the receiver CDR to start recovering valid data after the rx_is_lockedtodatasignal goes high when the CDR is  
functioning in the manual mode.  
tLTR_LTD_manual is the time the receiver CDR must be kept in lock to reference (LTR) mode after the rx_is_lockedtorefsignal goes high when the  
CDR is functioning in the manual mode.  
(53)  
(54)  
The rate match FIFO supports only up to 300 ppm.  
The Quartus Prime software allows AC gain setting = 3 for design with data rate between 611 Mbps and 1.25 Gbps only.  
Arria V GX, GT, SX, and ST Device Datasheet  
Send Feedback  
Altera Corporation  
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