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5AGXMA1D6F27C6N 参数 Datasheet PDF下载

5AGXMA1D6F27C6N图片预览
型号: 5AGXMA1D6F27C6N
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 500MHz, 75000-Cell, CMOS, PBGA672, ROHS COMPLIANT, FBGA-672]
分类和应用: 可编程逻辑
文件页数/大小: 182 页 / 2239 K
品牌: INTEL [ INTEL ]
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AV-51002  
2015.12.16  
2-50  
Soft CDR Mode High-Speed I/O Specifications  
Table 2-43: DPA Lock Time Specifications for Arria V GZ Devices  
The DPA lock time is for one channel.  
One data transition is defined as a 0-to-1 or 1-to-0 transition.  
The DPA lock time stated in this table applies to both commercial and industrial grade.  
Standard  
Training Pattern  
Number of Data Transitions Number of Repetitions per  
in One Repetition of the  
Training Pattern  
Maximum  
256 Data Transitions (200)  
SPI-4  
00000000001111111111  
00001111  
2
2
4
8
8
128  
128  
64  
640 data transitions  
640 data transitions  
640 data transitions  
640 data transitions  
640 data transitions  
Parallel Rapid I/O  
Miscellaneous  
10010000  
10101010  
32  
01010101  
32  
Soft CDR Mode High-Speed I/O Specifications  
Table 2-44: High-Speed I/O Specifications for Arria V GZ Devices  
When J = 3 to 10, use the serializer/deserializer (SERDES) block.  
When J = 1 or 2, bypass the SERDES block.  
C3, I3L  
C4, I4  
Symbol  
Conditions  
Unit  
Max  
Min  
Typ  
Max  
Min  
Typ  
Soft-CDR ppm tolerance  
300  
300  
ppm  
(200)  
This is the number of repetitions for the stated training pattern to achieve the 256 data transitions.  
Arria V GZ Device Datasheet  
Send Feedback  
Altera Corporation  
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