AV-51002
2015.12.16
2-46
Transmitter High-Speed I/O Specifications
Transmitter High-Speed I/O Specifications
Table 2-40: Transmitter High-Speed I/O Specifications for Arria V GZ Devices
When J = 3 to 10, use the serializer/deserializer (SERDES) block.
When J = 1 or 2, bypass the SERDES block.
C3, I3L
Typ
C4, I4
Typ
Symbol
Conditions
Unit
Min
Max
Min
Max
(183)
(183)
SERDES factor J = 3 to 10
—
1250
—
1050
Mbps
(181) (182)
,
(183)
(183)
SERDES factor J ≥ 4
—
1600
—
1250
Mbps
LVDS TX with DPA
True Differential I/O
Standards - fHSDR (data rate)
(184) (185) (186) (187)
,
,
,
(183)
(183)
(188)
(188)
(183)
(183)
(188)
(188)
SERDES factor J = 2,
uses DDR Registers
—
—
—
—
Mbps
Mbps
SERDES factor J = 1,
uses SDR Register
(181)
(182)
If the receiver with DPA enabled and transmitter are using shared PLLs, the minimum data rate is 150 Mbps.
The FMAX specification is based on the fast clock used for serial data. The interface FMAX is also dependent on the parallel clock domain which is
design dependent and requires timing analysis.
(183)
The minimum specification depends on the clock source (for example, the PLL and clock pin) and the clock routing resource (global, regional, or
local) that you use. The I/O differential buffer and input register do not have a minimum toggle rate.
Arria V GZ RX LVDS will need DPA. For Arria V GZ TX LVDS, the receiver side component must have DPA.
Requires package skew compensation with PCB trace length.
Do not mix single-ended I/O buffer within LVDS I/O bank.
Chip-to-chip communication only with a maximum load of 5 pF.
The maximum ideal data rate is the SERDES factor (J) x the PLL maximum output frequency (fOUT) provided you can close the design timing and
the signal integrity simulation is clean.
(184)
(185)
(186)
(187)
(188)
Arria V GZ Device Datasheet
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