AV-51002
2015.12.16
2-48
Receiver High-Speed I/O Specifications
Receiver High-Speed I/O Specifications
Table 2-41: Receiver High-Speed I/O Specifications for Arria V GZ Devices
When J = 3 to 10, use the serializer/deserializer (SERDES) block.
When J = 1 or 2, bypass the SERDES block.
C3, I3L
Typ
C4, I4
Typ
—
Symbol
Conditions
Unit
Min
Max
Min
Max
SERDES factor J = 3 to 10
150
—
1250
150
1050
Mbps
(191) (192) (193) (194) (195) (196)
,
,
,
,
,
SERDES factor J ≥ 4
150
—
1600
150
—
1250
Mbps
LVDS RX with DPA
True Differential I/O
Standards - fHSDRDPA
(data rate)
(192) (194) (195) (196)
,
,
,
(197)
(197)
(198)
(198)
(197)
(197)
(198)
(198)
SERDES factor J = 2,
uses DDR Registers
—
—
—
—
Mbps
Mbps
SERDES factor J = 1,
uses SDR Register
(191)
The FMAX specification is based on the fast clock used for serial data. The interface FMAX is also dependent on the parallel clock domain which is
design dependent and requires timing analysis.
Arria V GZ RX LVDS will need DPA. For Arria V GZ TX LVDS, the receiver side component must have DPA.
Arria V GZ LVDS serialization and de-serialization factor needs to be x4 and above.
Requires package skew compensation with PCB trace length.
Do not mix single-ended I/O buffer within LVDS I/O bank.
Chip-to-chip communication only with a maximum load of 5 pF.
The minimum specification depends on the clock source (for example, the PLL and clock pin) and the clock routing resource (global, regional, or
local) that you use. The I/O differential buffer and input register do not have a minimum toggle rate.
The maximum ideal data rate is the SERDES factor (J) x the PLL maximum output frequency (fOUT) provided you can close the design timing and
the signal integrity simulation is clean.
(192)
(193)
(194)
(195)
(196)
(197)
(198)
Arria V GZ Device Datasheet
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