AV-51002
2015.12.16
2-49
DPA Mode High-Speed I/O Specifications
C3, I3L
Typ
—
C4, I4
Symbol
Conditions
Unit
Min
Max
Min
Typ
—
Max
(197)
(199)
(197)
(199)
SERDES factor J = 3 to 10
Mbps
Mbps
(197)
(197)
(198)
(198)
(197)
(197)
(198)
(198)
SERDES factor J = 2,
uses DDR Registers
—
—
fHSDR (data rate)
SERDES factor J = 1,
uses SDR Register
—
—
Mbps
DPA Mode High-Speed I/O Specifications
Table 2-42: High-Speed I/O Specifications for Arria V GZ Devices
When J = 3 to 10, use the serializer/deserializer (SERDES) block.
When J = 1 or 2, bypass the SERDES block.
C3, I3L
C4, I4
Typ
Symbol
Conditions
Unit
Min
Typ
Max
Min
Max
DPA run length
—
—
—
10000
—
—
10000
UI
Figure 2-3: DPA Lock Time Specification with DPA PLL Calibration Enabled
rx_reset
DPA Lock Time
256 data
rx_dpa_locked
256 data
transitions
96 slow
96 slow
256 data
clock cycles transitions
clock cycles transitions
(199)
You can estimate the achievable maximum data rate for non-DPA mode by performing link timing closure analysis. You must consider the board
skew margin, transmitter delay margin, and receiver sampling margin to determine the maximum data rate supported.
Arria V GZ Device Datasheet
Send Feedback
Altera Corporation
INTEL [ INTEL ]
