AV-51002
2015.12.16
2-45
Periphery Performance
Periphery Performance
I/O performance supports several system interfaces, such as the LVDS high-speed I/O interface, external memory interface, and the PCI/PCI-X
bus interface. General-purpose I/O standards such as 3.3-, 2.5-, 1.8-, and 1.5-LVTTL/LVCMOS are capable of a typical 167 MHz and 1.2-
LVCMOS at 100 MHz interfacing frequency with a 10 pF load.
Note: The actual achievable frequency depends on design- and system-specific factors. Ensure proper timing closure in your design and perform
HSPICE/IBIS simulations based on your specific design and system setup to determine the maximum achievable frequency in your system.
High-Speed I/O Specification
High-Speed Clock Specifications
Table 2-39: High-Speed Clock Specifications for Arria V GZ Devices
When J = 3 to 10, use the serializer/deserializer (SERDES) block.
When J = 1 or 2, bypass the SERDES block.
C3, I3L
Typ
C4, I4
Typ
Symbol
Conditions
Unit
Min
Max
Min
Max
fHSCLK_in (input clock
frequency) True Differential
I/O Standards (178)
Clock boost factor
W = 1 to 40 (179)
5
—
625
5
—
—
—
—
525
MHz
fHSCLK_in (input clock
frequency) Single Ended I/O
Standards
Clock boost factor
W = 1 to 40 (179)
5
5
5
—
—
—
625
420
5
5
5
525
420
MHz
MHz
MHz
fHSCLK_in (input clock
frequency) Single Ended I/O
Standards
Clock boost factor
W = 1 to 40 (179)
fHSCLK_OUT (output clock
frequency)
—
625 (180)
525 (180)
(178)
(179)
(180)
This only applies to DPA and soft-CDR modes.
Clock Boost Factor (W) is the ratio between the input data rate to the input clock rate.
This is achieved by using the LVDS clock network.
Arria V GZ Device Datasheet
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