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5AGXMA1D6F27C6N 参数 Datasheet PDF下载

5AGXMA1D6F27C6N图片预览
型号: 5AGXMA1D6F27C6N
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 500MHz, 75000-Cell, CMOS, PBGA672, ROHS COMPLIANT, FBGA-672]
分类和应用: 可编程逻辑
文件页数/大小: 182 页 / 2239 K
品牌: INTEL [ INTEL ]
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AV-51002  
2015.12.16  
2-42  
DSP Block Specifications  
Symbol  
Parameter  
Min  
128  
Typ  
8388608  
5.96  
Max  
2147483648  
0.023  
Unit  
kVALUE  
fRES  
Numerator of Fraction  
Resolution of VCO frequency (fINPFD = 100 MHz)  
390625  
Hz  
Related Information  
Duty Cycle Distortion (DCD) Specifications on page 2-55  
DLL Range Specifications on page 2-53  
DSP Block Specifications  
Table 2-35: DSP Block Performance Specifications for Arria V GZ Devices  
Performance  
Mode  
Unit  
C3, I3L  
C4  
I4  
Modes using One DSP Block  
Three 9 × 9  
480  
480  
480  
400  
400  
400  
400  
400  
420  
MHz  
MHz  
MHz  
MHz  
MHz  
MHz  
MHz  
MHz  
One 18 × 18  
420  
420  
400  
400  
Two partial 18 × 18 (or 16 × 16)  
One 27 × 27  
350  
350  
350  
350  
350  
One 36 × 18  
One sum of two 18 × 18 (One sum of two 16 × 16)  
One sum of square  
One 18 × 18 plus 36 (a × b) + c  
Modes using Two DSP Blocks  
Three 18 × 18  
400  
380  
350  
300  
MHz  
MHz  
One sum of four 18 × 18  
Arria V GZ Device Datasheet  
Send Feedback  
Altera Corporation  
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