Processor Configuration Registers
2.6.14
SSTS—Secondary Status Register
SSTS is a 16-bit status register that reports the occurrence of error conditions
associated with secondary side (that is, PCI Express-G side) of the "virtual" PCI-PCI
bridge embedded within the processor.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
0/1/0–2/PCI
1E–1Fh
0000h
RW1C, RO
16 bits
00h
Size:
BIOS Optimal Default
Reset
Value
RST/
PWR
Bit
Access
Description
Detected Parity Error (DPE)
This bit is set by the Secondary Side for a Type 1 Configuration
Space header device whenever it receives a Poisoned TLP,
regardless of the state of the Parity Error Response Enable bit in
the Bridge Control Register.
15
RW1C
0b
0b
0b
Uncore
Uncore
Uncore
Received System Error (RSE)
This bit is set when the Secondary Side for a Type 1 configuration
space header device receives an ERR_FATAL or ERR_NONFATAL.
14
13
RW1C
RW1C
Received Master Abort (RMA)
This bit is set when the Secondary Side for Type 1 Configuration
Space Header Device (for requests initiated by the Type 1 Header
Device itself) receives a Completion with Unsupported Request
Completion Status.
Received Target Abort (RTA)
This bit is set when the Secondary Side for Type 1 Configuration
Space Header Device (for requests initiated by the Type 1 Header
Device itself) receives a Completion with Completer Abort
Completion Status.
12
11
RW1C
0b
0b
Uncore
Uncore
Signaled Target Abort (STA)
Not Applicable or Implemented. Hardwired to 0. The processor
does not generate Target Aborts (The root port will never
complete a request using the Completer Abort Completion
status).
RO
UR detected inside the processor (such as in iMPH/MC will be
reported in primary side status)
DEVSELB Timing (DEVT)
Not Applicable or Implemented. Hardwired to 0.
10:9
8
RO
00b
0b
Uncore
Uncore
Uncore
Master Data Parity Error (SMDPE)
When set indicates that the processor received across the link
(upstream) a Read Data Completion Poisoned TLP (EP=1). This
bit can only be set when the Parity Error Enable bit in the Bridge
Control register is set.
RW1C
Fast Back-to-Back (FB2B)
Not Applicable or Implemented. Hardwired to 0.
7
6
RO
RO
RO
RO
0b
0h
0b
0h
Reserved (RSVD)
66/60 MHz capability (CAP66)
Not Applicable or Implemented. Hardwired to 0.
5
Uncore
4:0
Reserved (RSVD)
96
Datasheet, Volume 2
INTEL [ INTEL ]
