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326769-002 参数 Datasheet PDF下载

326769-002图片预览
型号: 326769-002
PDF下载: 下载PDF文件 查看货源
内容描述: 移动第三代英特尔®科雷亚?? ¢处理器家族 [Mobile 3rd Generation Intel® Core™ Processor Family]
分类和应用:
文件页数/大小: 342 页 / 2513 K
品牌: INTEL [ INTEL ]
 浏览型号326769-002的Datasheet PDF文件第88页浏览型号326769-002的Datasheet PDF文件第89页浏览型号326769-002的Datasheet PDF文件第90页浏览型号326769-002的Datasheet PDF文件第91页浏览型号326769-002的Datasheet PDF文件第93页浏览型号326769-002的Datasheet PDF文件第94页浏览型号326769-002的Datasheet PDF文件第95页浏览型号326769-002的Datasheet PDF文件第96页  
Processor Configuration Registers  
2.6.5  
RID—Revision Identification Register  
This register contains the revision number of the processor root port. These bits are  
read only and writes to this register have no effect.  
B/D/F/Type:  
Address Offset:  
Reset Value:  
Access:  
0/1/0–2/PCI  
8h  
00h  
RO-FW  
8 bits  
Size:  
Reset  
Value  
RST/  
PWR  
Bit  
Access  
Description  
Revision Identification Number (RID)  
This is an 8-bit value that indicates the revision identification  
7:0  
RO-FW  
0h  
Uncore  
number for the root port. Refer to the Mobile 3rd Generation  
®
Intel Core™ Processor Family Specification Update for the value  
of the RID register.  
2.6.6  
CC—Class Code Register  
This register identifies the basic function of the device, a more specific sub-class, and a  
register-specific programming interface.  
B/D/F/Type:  
Address Offset:  
Reset Value:  
Access:  
0/1/0–2/PCI  
9–Bh  
060400h  
RO  
Size:  
24 bits  
Reset  
Value  
RST/  
PWR  
Bit  
Access  
Description  
Base Class Code (BCC)  
23:16  
RO  
06h  
04h  
Uncore  
Uncore  
This field indicates the base class code for this device. This code  
has the value 06h indicating a Bridge device.  
Sub-Class Code (SUBCC)  
This field indicates the sub-class code for this device. The code is  
04h indicating a PCI to PCI Bridge.  
15:8  
7:0  
RO  
RO  
Programming Interface (PI)  
This field indicates the programming interface of this device. This  
value does not specify a particular register set layout and  
provides no practical use for this device.  
00h  
Uncore  
2.6.7  
CL—Cache Line Size Register  
B/D/F/Type:  
Address Offset:  
Reset Value:  
Access:  
0/1/0–2/PCI  
Ch  
00h  
RW  
8 bits  
Size:  
Reset  
Value  
RST/  
PWR  
Bit  
Access  
Description  
Cache Line Size (CLS)  
Implemented by PCI Express devices as a read-write field for  
legacy compatibility purposes but has no impact on any PCI  
Express device functionality.  
7:0  
RW  
00h  
Uncore  
92  
Datasheet, Volume 2