Processor Configuration Registers
2.6.8
HDR—Header Type Register
This register identifies the header layout of the configuration space. No physical
register exists at this location.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
0/1/0–2/PCI
Eh
81h
RO
8 bits
Size:
Reset
Value
RST/
PWR
Bit
Access
Description
Header Type Register (HDR)
Device 1 returns 81h to indicate that this is a multi function
device with bridge header layout.
7:0
RO
81h
Uncore
Device 6 returns 01h to indicate that this is a single function
device with bridge header layout.
2.6.9
PBUSN—Primary Bus Number Register
This register identifies that this "virtual" Host-PCI Express* bridge is connected to PCI
bus 0.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
0/1/0–2/PCI
18h
00h
RO
Size:
8 bits
Reset
Value
RST/
PWR
Bit
Access
Description
Primary Bus Number (BUSN)
Configuration software typically programs this field with the
number of the bus on the primary side of the bridge. Since the
processor root port is an internal device and its primary bus is
always 0, these bits are read only and are hardwired to 0.
7:0
RO
00h
Uncore
2.6.10
SBUSN—Secondary Bus Number Register
This register identifies the bus number assigned to the second bus side of the "virtual"
bridge; that is, to PCI Express-G. This number is programmed by the PCI configuration
software to allow mapping of configuration cycles to PCI Express-G.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
0/1/0–2/PCI
19h
00h
RW
8 bits
Size:
Reset
Value
RST/
PWR
Bit
Access
Description
Secondary Bus Number (BUSN)
7:0
RW
00h
Uncore
This field is programmed by configuration software with the bus
number assigned to PCI Express-G.
Datasheet, Volume 2
93
INTEL [ INTEL ]
