Processor Configuration Registers
®
2.5.19
MESEG_BASE—Intel Management Engine Base Address
Register
This register determines the Base Address register of the memory range that is pre-
allocated to the Intel Management Engine. Together with the MESEG_MASK register it
controls the amount of memory allocated to the ME.
This register must be initialized by the configuration software. For the purpose of
address decode, address bits A[19:0] are assumed to be 0. Thus, the bottom of the
defined memory address range will be aligned to a 1 MB boundary.
This register is locked by Intel TXT.
Note:
BIOS must program MESEG_BASE and MESEG_MASK so that Intel ME stolen Memory is
carved out from TOM.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
0/0/0/PCI
70–77h
0000007FFFF00000h
RW-L
64 bits
000000000000h
Size:
BIOS Optimal Default
Reset
Value
RST/
PWR
Bit
Access
Description
63:39
RO
0h
7FFFFh
0h
Reserved (RSVD)
ME UMA Memory Base Address (MEBASE)
This field corresponds to A[38:20] of the base address memory
range that is allocated to the ME.
38:20
19:0
RW-L
RO
Uncore
Reserved (RSVD)
Datasheet, Volume 2
63
INTEL [ INTEL ]
