Processor Configuration Registers
2.5.18
DMIBAR—Root Complex Register Range Base Address
Register
This is the base address for the Root Complex configuration space. This window of
addresses contains the Root Complex Register set for the PCI Express Hierarchy
associated with the Host Bridge. There is no physical memory within this 4 KB window
that can be addressed. The 4 KB reserved by this register does not alias to any PCI 2.3
compliant memory mapped space. On reset, the Root Complex configuration space is
disabled and must be enabled by writing a 1 to DMIBAREN [Device 0, offset 68h, bit 0].
All the bits in this register are locked in Intel TXT mode.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
0/0/0/PCI
68–6Fh
0000000000000000h
RW
64 bits
000000000h
Size:
BIOS Optimal Default
Reset
Value
RST/
PWR
Bit
Access
Description
63:39
RO
0h
Reserved (RSVD)
DMI Base Address (DMIBAR)
This field corresponds to bits 38:12 of the base address DMI
configuration space. BIOS will program this register resulting in a
base address for a 4 KB block of contiguous memory address
space. This register ensures that a naturally aligned 4 KB space is
allocated within the first 512 GB of addressable memory space.
System Software uses this base address to program the DMI
register set. All the bits in this register are locked in Intel TXT
mode.
38:12
RW
0000000h
Uncore
11:1
0
RO
0h
0b
Reserved (RSVD)
DMIBAR Enable (DMIBAREN)
0 = Disable. DMIBAR is disabled and does not claim any memory
1 = Enable. DMIBAR memory mapped accesses are claimed and
decoded appropriately
RW
Uncore
This register is locked by Intel TXT.
62
Datasheet, Volume 2
INTEL [ INTEL ]
