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326769-002 参数 Datasheet PDF下载

326769-002图片预览
型号: 326769-002
PDF下载: 下载PDF文件 查看货源
内容描述: 移动第三代英特尔®科雷亚?? ¢处理器家族 [Mobile 3rd Generation Intel® Core™ Processor Family]
分类和应用:
文件页数/大小: 342 页 / 2513 K
品牌: INTEL [ INTEL ]
 浏览型号326769-002的Datasheet PDF文件第305页浏览型号326769-002的Datasheet PDF文件第306页浏览型号326769-002的Datasheet PDF文件第307页浏览型号326769-002的Datasheet PDF文件第308页浏览型号326769-002的Datasheet PDF文件第310页浏览型号326769-002的Datasheet PDF文件第311页浏览型号326769-002的Datasheet PDF文件第312页浏览型号326769-002的Datasheet PDF文件第313页  
Processor Configuration Registers  
2.21  
Default PEG/DMI VTd Remapping Engine  
Registers  
Table 2-24. Default PEG/DMI VTd Remapping Engine Register Address Map (Sheet 1 of 2)  
Address  
Offset  
Symbol  
Register Name  
Reset Value  
Access  
0–3h  
4–7h  
VER_REG  
RSVD  
Version Register  
00000010h  
0h  
RO  
RO  
Reserved  
Capability Register  
00C9008020660  
262h  
8–Fh  
CAP_REG  
RO  
Extended Capability Register  
0000000000F01  
0DAh  
10–17h  
ECAP_REG  
RO-V, RO  
18–1Bh  
1C–1Fh  
GCMD_REG  
GSTS_REG  
Global Command Register  
Global Status Register  
00000000h  
00000000h  
RO, WO  
RO, RO-V  
Root-Entry Table Address Register  
0000000000000  
000h  
20–27h  
RTADDR_REG  
RW  
Context Command Register  
0000000000000  
000h  
28–2Fh  
30–33h  
34–37h  
CCMD_REG  
RSVD  
RW-V, RW, RO-V  
RO  
Reserved  
0h  
Fault Status Register  
RW1CS, ROS-V,  
RO  
FSTS_REG  
00000000h  
38–3Bh  
3C–3Fh  
40–43h  
44–47h  
48–57h  
FECTL_REG  
FEDATA_REG  
FEADDR_REG  
FEUADDR_REG  
RSVD  
Fault Event Control Register  
Fault Event Data Register  
Fault Event Address Register  
Fault Event Upper Address Register  
Reserved  
80000000h  
00000000h  
00000000h  
00000000h  
0h  
RW, RO-V  
RW  
RW  
RW  
RO  
Advanced Fault Log Register  
0000000000000  
000h  
58–5Fh  
AFLOG_REG  
RO  
60–63h  
64–67h  
68–6Bh  
6C–6Fh  
RSVD  
Reserved  
0h  
RO  
RW, RO-V  
RW  
PMEN_REG  
PLMBASE_REG  
Protected Memory Enable Register  
Protected Low-Memory Base Register  
00000000h  
00000000h  
00000000h  
PLMLIMIT_REG Protected Low-Memory Limit Register  
RW  
Protected High-Memory Base  
0000000000000  
000h  
70–77h  
78–7Fh  
80–87h  
88–8Fh  
PHMBASE_REG  
Register  
RW  
RW  
Protected High-Memory Limit  
0000000000000  
000h  
PHMLIMIT_REG  
Register  
Invalidation Queue Head Register  
IQH_REG  
0000000000000  
000h  
RO-V  
RW-L  
Invalidation Queue Tail Register  
IQT_REG  
0000000000000  
000h  
Invalidation Queue Address Register  
IQA_REG  
0000000000000  
000h  
90–97h  
98–9Bh  
9C–9Fh  
RW-L  
RO  
RSVD  
Reserved  
0h  
Invalidation Completion Status  
Register  
ICS_REG  
00000000h  
RW1CS  
A0–A3h  
A4–A7h  
A8–ABh  
IECTL_REG  
IEDATA_REG  
IEADDR_REG  
Invalidation Event Control Register  
Invalidation Event Data Register  
Invalidation Event Address Register  
80000000h  
00000000h  
00000000h  
RW-L, RO-V  
RW-L  
RW-L  
Datasheet, Volume 2  
309