Processor Configuration Registers
2.20
PXPEPBAR Registers
Table 2-23. PXPEPBAR Address Map
Address
Register Symbol
Offset
Register Name
Reset Value
Access
0–13h
14–17h
18–9Fh
RSVD
EPVC0RCTL
RSVD
Reserved
0h
800000FFh
—
RO
RO, RW
—
EP VC 0 Resource Control
Reserved
2.20.1
EPVC0RCTL—EP VC 0 Resource Control Register
This register controls the resources associated with Egress Port Virtual Channel 0.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
0/0/0/PXPEPBAR
14–17h
800000FFh
RO, RW
32 bits
00000h
Size:
BIOS Optimal Default
Reset
Value
RST/
PWR
Bit
Access
Description
31:20
RO
0h
000b
0h
Reserved (RSVD)
Port Arbitration Select (PAS)
This field configures the VC resource to provide a particular Port
Arbitration service. The value of 0h corresponds to the bit
position of the only asserted bit in the Port Arbitration Capability
field.
19:17
16:0
RW
RO
Uncore
Reserved (RSVD)
308
Datasheet, Volume 2
INTEL [ INTEL ]
