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326769-002 参数 Datasheet PDF下载

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型号: 326769-002
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内容描述: 移动第三代英特尔®科雷亚?? ¢处理器家族 [Mobile 3rd Generation Intel® Core™ Processor Family]
分类和应用:
文件页数/大小: 342 页 / 2513 K
品牌: INTEL [ INTEL ]
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Processor Configuration Registers  
2.18.26 IEUADDR_REG—Invalidation Event Upper Address  
Register  
This register specifies the Invalidation Event interrupt message upper address.  
B/D/F/Type:  
Address Offset:  
Reset Value:  
Access:  
0/0/0/GFXVTBAR  
AC–AFh  
00000000h  
RW-L  
32 bits  
Size:  
Reset  
Value  
RST/  
PWR  
Bit  
Access  
Description  
Message Upper Address (MUA)  
Hardware implementations supporting Queued Invalidations and  
Extended Interrupt Mode are required to implement this register.  
31:0  
RW-L  
00000000h  
Uncore  
Hardware implementations not supporting Queued Invalidations  
or Extended Interrupt Mode may treat this field as RsvdZ.  
2.18.27 IRTA_REG—Interrupt Remapping Table Address Register  
This register provides the base address of Interrupt remapping table. This register is  
treated as RsvdZ by implementations reporting Interrupt Remapping (IR) as not  
supported in the Extended Capability register.  
B/D/F/Type:  
Address Offset:  
Reset Value:  
Access:  
0/0/0/GFXVTBAR  
B8–BFh  
0000000000000000h  
RW-L  
64 bits  
00000000h  
Size:  
BIOS Optimal Default  
Reset  
Value  
RST/  
PWR  
Bit  
Access  
Description  
63:39  
RO  
0h  
Reserved (RSVD)  
Interrupt Remapping Table Address (IRTA)  
This field points to the base of 4 KB aligned interrupt remapping  
table.  
Hardware ignores and does not implement bits 63:HAW, where  
HAW is the host address width.  
38:12  
RW-L  
0000000h  
Uncore  
Uncore  
Reads of this field returns value that was last programmed to it.  
11:4  
3:0  
RO  
0h  
0h  
Reserved (RSVD)  
Size (S)  
This field specifies the size of the interrupt remapping table. The  
number of entries in the interrupt remapping table is 2^(X+1),  
where X is the value programmed in this field.  
RW-L  
Datasheet, Volume 2  
289