Processor Configuration Registers
2.18.24 IEDATA_REG—Invalidation Event Data Register
This register specifies the Invalidation Event interrupt message data.
This register is treated as RsvdZ by implementations reporting Queued Invalidation
(QI) as not supported in the Extended Capability register.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
0/0/0/GFXVTBAR
A4–A7h
00000000h
RW-L
32 bits
Size:
Reset
Value
RST/
PWR
Bit
Access
RW-L
Description
Extended Interrupt Message Data (EIMD)
This field is valid only for implementations supporting 32-bit
interrupt data fields.
Hardware implementations supporting only 16-bit interrupt data
treat this field as Rsvd.
31:16
15:0
0000h
0000h
Uncore
Uncore
Interrupt Message data (IMD)
Data value in the interrupt request.
RW-L
2.18.25 IEADDR_REG—Invalidation Event Address Register
This register specifies the Invalidation Event Interrupt message address.
This register is treated as RsvdZ by implementations reporting Queued Invalidation
(QI) as not supported in the Extended Capability register.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
0/0/0/GFXVTBAR
A8–ABh
00000000h
RW-L
32 bits
0h
Size:
BIOS Optimal Default
Reset
Value
RST/
PWR
Bit
Access
Description
Message address (MA)
00000000
h
When fault events are enabled, the contents of this register
specify the DWord-aligned address (bits 31:2) for the interrupt
request.
31:2
1:0
RW-L
RO
Uncore
0h
Reserved (RSVD)
288
Datasheet, Volume 2
INTEL [ INTEL ]
