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326769-002 参数 Datasheet PDF下载

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型号: 326769-002
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内容描述: 移动第三代英特尔®科雷亚?? ¢处理器家族 [Mobile 3rd Generation Intel® Core™ Processor Family]
分类和应用:
文件页数/大小: 342 页 / 2513 K
品牌: INTEL [ INTEL ]
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Processor Configuration Registers  
2.18.23 IECTL_REG—Invalidation Event Control Register  
This register specifies the invalidation event interrupt control bits.  
This register is treated as RsvdZ by implementations reporting Queued Invalidation  
(QI) as not supported in the Extended Capability register.  
B/D/F/Type:  
Address Offset:  
Reset Value:  
Access:  
0/0/0/GFXVTBAR  
A0–A3h  
80000000h  
RW-L, RO-V  
32 bits  
Size:  
BIOS Optimal Default  
00000000h  
Reset  
Value  
RST/  
PWR  
Bit  
Access  
Description  
Interrupt Mask (IM)  
0 = No masking of interrupt. When an invalidation event  
condition is detected, hardware issues an interrupt message  
(using the Invalidation Event Data & Invalidation Event  
Address register values).  
31  
RW-L  
1b  
Uncore  
1 = This is the value on reset. Software may mask interrupt  
message generation by setting this field. Hardware is  
prohibited from sending the interrupt message when this  
field is set.  
Interrupt Pending (IP)  
Hardware sets the IP field whenever it detects an interrupt  
condition. Interrupt condition is defined as:  
An Invalidation Wait Descriptor with Interrupt Flag (IF) field  
set completed, setting the IWC field in the Invalidation  
Completion Status register.  
If the IWC field in the Invalidation Completion Status register  
was already set at the time of setting this field, it is not  
treated as a new interrupt condition.  
The IP field is kept set by hardware while the interrupt message  
is held pending. The interrupt message could be held pending  
due to interrupt mask (IM field) being set, or due to other  
transient hardware conditions. The IP field is cleared by hardware  
as soon as the interrupt message pending condition is serviced.  
This could be due to either:  
30  
RO-V  
0b  
Uncore  
Hardware issuing the interrupt message due to either change  
in the transient hardware condition that caused interrupt  
message to be held pending or due to software clearing the  
IM field.  
Software servicing the IWC field in the Invalidation  
Completion Status register.  
29:0  
RO  
0h  
Reserved (RSVD)  
Datasheet, Volume 2  
287