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326769-002 参数 Datasheet PDF下载

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型号: 326769-002
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内容描述: 移动第三代英特尔®科雷亚?? ¢处理器家族 [Mobile 3rd Generation Intel® Core™ Processor Family]
分类和应用:
文件页数/大小: 342 页 / 2513 K
品牌: INTEL [ INTEL ]
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Processor Configuration Registers  
2.18.21 IQA_REG—Invalidation Queue Address Register  
This register configures the base address and size of the invalidation queue. This  
register is treated as RsvdZ by implementations reporting Queued Invalidation (QI) as  
not supported in the Extended Capability register.  
B/D/F/Type:  
Address Offset:  
Reset Value:  
Access:  
0/0/0/GFXVTBAR  
90–97h  
0000000000000000h  
RW-L  
64 bits  
000000000h  
Size:  
BIOS Optimal Default  
Reset  
Value  
RST/  
PWR  
Bit  
Access  
Description  
63:39  
RO  
0h  
Reserved (RSVD)  
Invalidation Queue Base Address (IQA)  
This field points to the base of 4 KB aligned invalidation request  
queue. Hardware ignores and does not implement bits 63:HAW,  
where HAW is the host address width.  
Reads of this field return the value that was last programmed to  
it.  
38:12  
RW-L  
0000000h  
Uncore  
Uncore  
11:3  
2:0  
RO  
0h  
0h  
Reserved (RSVD)  
Queue Size (QS)  
This field specifies the size of the invalidation request queue. A  
value of X in this field indicates an invalidation request queue of  
(2^X) 4 KB pages. The number of entries in the invalidation  
queue is 2^(X + 8).  
RW-L  
2.18.22 ICS_REG—Invalidation Completion Status Register  
This register reports completion status of invalidation wait descriptor with Interrupt  
Flag (IF) set.  
This register is treated as RsvdZ by implementations reporting Queued Invalidation  
(QI) as not supported in the Extended Capability register.  
B/D/F/Type:  
Address Offset:  
Reset Value:  
Access:  
0/0/0/GFXVTBAR  
9C–9Fh  
00000000h  
RW1CS  
32 bits  
00000000h  
Size:  
BIOS Optimal Default  
Reset  
Value  
RST/  
PWR  
Bit  
Access  
Description  
31:1  
RO  
0h  
Reserved (RSVD)  
Invalidation Wait Descriptor Complete (IWC)  
This bit indicates completion of Invalidation Wait Descriptor  
with Interrupt Flag (IF) field set. Hardware implementations not  
supporting queued invalidations implement this field as RsvdZ.  
0
RW1CS  
0b  
Powergood  
286  
Datasheet, Volume 2