Processor Configuration Registers
2.17.2
PM_CMD_PWR—Power Management Command Power
Register
This register defines the power contribution of each command – ACT+PRE, CAS-read,
and CAS write. Assumption is that the ACT is always followed by a PRE (although not
immediately), and REF commands are issued in a fixed rate and there is no need to
count them. The register has 3 8-bit fields.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
0/0/0/MCHBAR_MCBCAST
4F84–4F87h
00000000h
RW-LV
32 bits
00h
Size:
BIOS Optimal Default
Reset
Value
RST/
PWR
Bit
Access
Description
31:24
23:16
15:8
RO
0h
Reserved (RSVD)
RW-LV
RW-LV
00h
00h
Uncore
Uncore
Power contribution of CAS Write command (PWR_CAS_W)
Power contribution of CAS Read command (PWR_CAS_R)
Power contribution of RAS command and PRE command
(PWR_RAS_PRE)
Power contribution of RAS command and PRE command. The
value should be the sum of the two commands, assuming that
each RAS command for a given page is followed by a PRE
command to the same page in the near future.
7:0
RW-LV
00h
Uncore
2.17.3
PM_BW_LIMIT_CONFIG—BW Limit Configuration Register
This register defines the BW throttling at temperature.
Note:
The field “BW_limit_tf may not be changed in run-time. Other fields may be changed in
run-time.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
0/0/0/MCHBAR_MCBCAST
4F88–4F8Bh
FFFF03FFh
RW-L
32 bits
Size:
BIOS Optimal Default
5F7003FFh
Reset
Value
RST/
PWR
Bit
Access
Description
BW limit when rank is hot (BW_limit_hot)
31:24
RW-L
FFh
Uncore
Uncore
Number of transactions allowed per rank when status of rank is
hot. Range: 0–255h
BW limit when rank is warm (BW_limit_warm)
Number of transactions allowed per rank when status of rank is
warm. Range: 0–255h
23:16
15:10
RW-L
RO
FFh
0h
Reserved (RSVD)
BW limit time frame (BW_limit_tf)
Time frame in which the BW limit is enforced, in DCLK cycles.
Range: 1–1023h
9:0
RW-L
3FFh
Uncore
Note: The field “BW_limit_tf may not be changed in run-time.
Datasheet, Volume 2
259
INTEL [ INTEL ]
