Processor Configuration Registers
Table 2-21. Integrated Graphics VTd Remapping Engine Register Address Map (Sheet 2 of
2)
Address
Offset
Register Symbol
Register Name
Reset Value
Access
Invalidation Event Upper Address
Register
AC–AFh
B0–B7h
B8–BFh
C0–FFh
IEUADDR_REG
RSVD
00000000h
0h
RW-L
RO
Reserved
Interrupt Remapping Table Address
Register
000000000
0000000h
IRTA_REG
RSVD
RW-L
RO
Reserved
0h
Invalidate Address Register
000000000
0000000h
100–107h
IVA_REG
RW
IOTLB Invalidate Register
020000000
0000000h
RO-V, RW,
RW-V
108–10Fh
110–1FFh
200–207h
IOTLB_REG
RSVD
Reserved
0h
RO
Fault Recording Low Register
000000000
0000000h
FRCDL_REG
ROS-V
Fault Recording High Register
0000000000
000000h
RO, RW1CS,
ROS-V
208–20Fh
210–FEFh
FF0–FF3h
FRCDH_REG
RSVD
Reserved
0h
RO
DMA Remap Engine Policy Control
RW-L, RO, RO-
KFW, RW-KL
VTPOLICY
00000000h
2.18.1
VER_REG—Version Register
This register reports the architecture version supported. Backward compatibility for the
architecture is maintained with new revision numbers, allowing software to load
remapping hardware drivers written for prior architecture versions.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
0/0/0/GFXVTBAR
0–3h
00000010h
RO
32 bits
000000h
Size:
BIOS Optimal Default
Reset
Value
RST/
PWR
Bit
31:8
7:4
Access
RO
Description
0h
Reserved (RSVD)
Major Version number (MAX)
Indicates supported architecture version.
RO
0001b
Uncore
Uncore
Minor Version number (MIN)
Indicates supported architecture minor version.
3:0
RO
0000b
Datasheet, Volume 2
261
INTEL [ INTEL ]
